OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

PCA9541APW/03,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45
PCA9541A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 24 April 2014 19 of 45
NXP Semiconductors
PCA9541A
2-to-1 I
2
C-bus master selector with interrupt logic and reset
8. Characteristics of the I
2
C-bus
The I
2
C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
8.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
are interpreted as control signals (see Figure 9
).
8.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line, while the clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the
STOP condition (P) (see Figure 10
).
Fig 9. Bit transfer
mba607
data line
stable;
data valid
change
of data
allowed
SDA
SCL
Fig 10. Definition of START and STOP conditions
mba608
SDA
SCL
P
STOP condition
S
START condition
PCA9541A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 24 April 2014 20 of 45
NXP Semiconductors
PCA9541A
2-to-1 I
2
C-bus master selector with interrupt logic and reset
8.3 System configuration
A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 11
).
8.4 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of 8 bits is followed by one acknowledge
bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the
master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold
times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Fig 11. System configuration
002aaa966
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
SDA
SCL
I
2
C-BUS
MULTIPLEXER
SLAVE
Fig 12. Acknowledgement on the I
2
C-bus
002aaa987
S
START
condition
9821
clock pulse for
acknowledgement
not acknowledge
acknowledge
data output
by transmitter
data output
by receiver
SCL from master
PCA9541A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 24 April 2014 21 of 45
NXP Semiconductors
PCA9541A
2-to-1 I
2
C-bus master selector with interrupt logic and reset
8.5 Bus transactions
Remark: If a third data byte is sent, it is not acknowledged by the PCA9541A.
Remark: If a fourth data byte is read, the first register is accessed.
Fig 13. Write to the Interrupt Enable and Control registers using the Auto-Increment (AI) bit
002aab607
1 1 1 A3 A2 A1 A0 0
slave address
R/W
S
START condition
A
acknowledge
from slave
00010000
command code register
auto
increment
A
acknowledge
from slave
A P
STOP
condition
A
acknowledge
from slave
acknowledge
from slave
data
Interrupt Enable (IE)
register
data control register
(CONTROL)
(1) xx = 00: Interrupt Enable register
xx = 01: Control register
xx = 10: INT register
(2) xx = 00: Control register
xx = 01: INT register
xx = 10: Interrupt Enable register
(3) xx = 00: INT register
xx = 01: Interrupt Enable register
xx = 10: Control register
Fig 14. Read the 3 registers using the Auto-Increment (AI) bit
002aab608
1 1 1 A3 A2 A1 A0 0
slave address
R/W
S
START condition
A
acknowledge
from slave
000100xx
command code register
access to register
xx = 00, 01, or 10
auto
increment
A
acknowledge
from slave
A P
STOP
condition
A
no acknowledge
from master
acknowledge
from master
(1) (2)
Sr
re-START
condition
1 1 1 A3 A2 A1 A0 1
slave address
R/W
A
acknowledge
from slave
A
acknowledge
from master
(3)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45

PCA9541APW/03,118

Mfr. #:
Buy PCA9541APW/03,118
Manufacturer:
NXP Semiconductors
Description:
I/O Controller Interface IC IC I2C 2:1 SELECTOR
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet