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PCA9541APW/03,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45
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PCA9541A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 24 April 2014 22 of 45
NXP Semiconductors
PCA9541A
2-to-1 I
2
C-bus master selector with interrupt logic and reset
(1) We assume that a read of the Control register was done by MASTER 0 before this sequence and that 000x 0101 was read (MASTER 1 controlling the bus).
Fig 15. Write to the Control register and switch from Channel 1 to Channel 0 (bus recovery/initialization requested)
002aab609
1 1 1 A3 A2 A1 A0 0
slave address
R/W
S
START condition
A
acknowledge
from slave
000AI0001
command code register
auto
increment
A
acknowledge
from slave
P
STOP
condition
A
acknowledge
from slave
data Control register
SDA_MST0
(1)
0 0 0 1 0 1 0 0
BUSINIT
BUSON
MYBUS
After the STOP condition
MASTER 1 is disconnected
from the downstream channel.
SCL_MST0
if the interrupt is not masked
(BUSLOSTMSK = 0)
INT1
123456789
SCL_SLAVE
SDA_SLAVE
A
STOP command
INT0
if the interrupt is not masked
(BUSINITMSK = 0)
PCA9541 has control of the bus
MASTER 0
has control
of the busMASTER 1 has control of the bus
MASTER 0 must wait for the 'bus free time' value
(between STOP and START) defined in the I
2
C-bus specification
before sending commands to the downstream devices.
PCA9541A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 24 April 2014 23 of 45
NXP Semiconductors
PCA9541A
2-to-1 I
2
C-bus master selector with interrupt logic and reset
(1) We assume that a read of the Control register was done by MASTER 0 before this sequence and that 000x 0101 was read
(MASTER 1 controlling the bus).
Fig 16. Write to the Control register and switch from Channel 1 to Channel 0 (bus recovery/initialization not
requested)
002aab610
1 1 1 A3 A2 A1 A0 0
slave address
R/W
S
START condition
A
acknowledge
from slave
000AI0001
command code register
auto
increment
A
acknowledge
from slave
P
STOP
condition
A
data Control register
SDA_MST0
(1)
0 0 0 0 0 1 0 0
After the STOP condition MASTER 1
is disconnected from the downstream
channel, and MASTER 0 is connected to
the downstream channel.
SCL_MST0
if the interrupt is not masked
(BUSLOSTMSK = 0)
INT1
INT0
if MASTER 1 was not idle at the switching moment
and the interrupt is not masked (BUSINITMSK = 0)
MASTER 0 has control of the busMASTER 1 has control of the bus
MASTER 0 must wait for the 'bus free time' value
(between STOP and START) defined in the I
2
C-bus specification
before sending commands to the downstream devices.
acknowledge
from slave
BUSINIT
BUSON
MYBUS
PCA9541A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 24 April 2014 24 of 45
NXP Semiconductors
PCA9541A
2-to-1 I
2
C-bus master selector with interrupt logic and reset
9. Application design-in information
9.1 Specific applications
The PCA9541A is a 2-to-1 I
2
C-bus master selector designed for dual master, high
reliability I
2
C-bus applications, where continuous maintenance and control monitoring is
required even if one master fails or its controller card is removed for maintenance. The
PCA9541A can also be used in other applications, such as where masters share the
same resource but cannot share the same bus, as a gatekeeper multiplexer in long single
bus applications or as a bus initialization/recovery device.
Fig 17. Typical application
PCA9541A
SCL_MST0
SDA_MST0
INT0
3.3 V
MASTER 0
002aae661
SCL0
SDA0
INT0 INT_IN
A3
A2
A1
V
DD
A0
V
SS
V
DD
RESET0
V
SS
SLAVE 1
SDA SCL
SLAVE 2
SDA SCL
INT
SLAVE 3
SDA SCL
SDA_SLAVE
SCL_SLAVE
SCL_MST1
SDA_MST1
INT1
3.3 V
MASTER 1
SCL1
SDA1
INT1
V
DD
RESET1
V
SS
RESET
SLAVE CARD
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45

PCA9541APW/03,118

Mfr. #:
Buy PCA9541APW/03,118
Manufacturer:
NXP Semiconductors
Description:
I/O Controller Interface IC IC I2C 2:1 SELECTOR
Lifecycle:
New from this manufacturer.
Delivery:
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