PCA9511A_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 19 August 2009 13 of 24
NXP Semiconductors
PCA9511A
Hot swappable I
2
C-bus and SMBus bus buffer
[1] This specification applies over the full operating temperature range.
[2] The enable time can slow considerably for some parts when temperature is < −20 °C.
[3] Delays that can occur after ENABLE and/or idle times have passed.
[4] Guaranteed by design, not production tested.
[5] I
trt(pu)
varies with temperature and V
CC
voltage, as shown in Section 11.1 “Typical performance characteristics”.
[6] Input pull-up voltage should not exceed power supply voltage in operating mode because the rise time accelerator will clamp the voltage
to the positive supply rail.
[7] The connection circuitry always regulates its output to a higher voltage than its input. The magnitude of this offset voltage as a function
of the pull-up resistor and V
CC
voltage is shown in Section 11.1 “Typical performance characteristics”.
[8] C
b
= total capacitance of one bus line in pF.
Input-output connection
V
offset
offset voltage 10 kΩ to V
CC
on SDA, SCL;
V
CC
= 3.3 V
[1][7][9]
0 110 175 mV
t
PLH
LOW to HIGH
propagation delay
SCL to SCL and SDA to SDA;
10 kΩ to V
CC
;
C
L
= 100 pF each side
-0-ns
t
PHL
HIGH to LOW
propagation delay
SCL to SCL and SDA to SDA;
10 kΩ to V
CC
;
C
L
= 100 pF each side
-70-ns
C
i(SCL/SDA)
SCL and SDA input
capacitance
[4]
- 57pF
V
OL
LOW-level output
voltage
V
I
= 0 V; SDAn, SCLn pins;
I
sink
= 3 mA; V
CC
= 2.7 V
[1]
0 - 0.4 V
I
LI
input leakage current SDAn, SCLn pins; V
CC
= 5.5 V −1-+1µA
System characteristics
f
SCL
SCL clock frequency
[4]
0 - 400 kHz
t
BUF
bus free time between a
STOP and START
condition
[4]
1.3 - - µs
t
HD;STA
hold time (repeated)
START condition
[4]
0.6 - - µs
t
SU;STA
set-up time for a
repeated
START condition
[4]
0.6 - - µs
t
SU;STO
set-up time for
STOP condition
[4]
0.6 - - µs
t
HD;DAT
data hold time
[4]
300 - - ns
t
SU;DAT
data set-up time
[4]
100 - - ns
t
LOW
LOW period of the
SCL clock
[4]
1.3 - - µs
t
HIGH
HIGH period of the
SCL clock
[4]
0.6 - - µs
t
f
fall time of both SDA and
SCL signals
[4][8]
20 + 0.1 × C
b
- 300 ns
t
r
rise time of both SDA
and SCL signals
[4][8]
20 + 0.1 × C
b
- 300 ns
Table 5. Characteristics
…continued
V
CC
= 2.7 V to 5.5 V; T
amb
=
−
40
°
C to +85 V; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
