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9EX21501AKILFT

P1-P3P4-P6P7-P9P10-P12P13-P15
IDT
®
15 Output PCIe G2/QPI Differential Buffer with 2:1 Input Mux 1578—01/18/11
9EX21501
15 Output PCIe G2/QPI Differential Buffer with 2:1 Input Mux
10
Datasheet
General SMBus serial interface information for the 9EX21501
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D4
(H)
• ICS clock will
acknowledge
• Controller (host) sends the beginning byte location = N
• ICS clock will
acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will
acknowledge
• Controller (host) starts sending
Byte N through
Byte N + X -1
• ICS clock will
acknowledge
each byte
one at a time
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D4
(H)
• ICS clock will
acknowledge
• Controller (host) sends the begining byte
location = N
• ICS clock will
acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D5
(H)
• ICS clock will
acknowledge
• ICS clock will send the data byte count = X
• ICS clock sends
Byte N + X -1
• ICS clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8)
.
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
ICS (Slave/Receiver)
T
WR
ACK
ACK
ACK
ACK
ACK
P
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
stoP bit
X Byte
Index Block Write Operation
Slave Address D4
(H)
Beginning Byte = N
WRite
starT bit
Controller (Host)
T starT bit
WR WRite
RT Repeat starT
RD ReaD
Beginning Byte N
Byte N + X - 1
N Not acknowledge
PstoP bit
ICS (Slave/Receiver)
Controller (Host)
X Byte
ACK
ACK
Data Byte Count = X
ACK
Slave Address D5
(H)
Index Block Read Operation
Slave Address D4
(H)
Beginning Byte = N
ACK
ACK
Note: SMBus address is selectable among 4 addresses.
See tabel on page 2.
IDT
®
15 Output PCIe G2/QPI Differential Buffer with 2:1 Input Mux 1578—01/18/11
9EX21501
15 Output PCIe G2/QPI Differential Buffer with 2:1 Input Mux
11
Datasheet
9EX21501 SMBus Addressing
`
SMB Adr: DC
9DB403/803
(DB400E/800E)
SMB Adr: D2
(CK410B+/CK509B)
SMB_A(1:0) = 10
SMB Adr: D8
SMB_A(1:0) = 11
SMB Adr: DA
SMB_A(1:0) = 00
SMB Adr: D4
SMB_A(1:0) = 01
SMB Adr: D6
SMB_A(2:0) = 100
SMB Adr: D8
SMB_A(2:0) = 101
SMB Adr: DA
SMB_A(2:0) = 110
SMB Adr: DC
SMB_A(2:0) = 111
SMB Adr: DE
SMB_A(2:0) = 000
SMB Adr: D0
SMB_A(2:0) = 001
SMB Adr: D2
SMB_A(2:0) = 010
SMB Adr: D4
SMB_A(2:0) = 011
SMB Adr: D6
OR
OR
OR
OR
OR
OR
9EX21501
(DB1200G/GS)
(DB1900G/GS)
(DB1200G/GS)
(DB1900G/GS)
(DB1200G/GS)
(DB1900G/GS)
9EX21501
(DB1200G/GS)
(DB1900G/GS)
(DB1200G/GS)
(DB1900G/GS)
(DB1200G/GS)
(DB1900G/GS)
(DB1200G/GS)
(DB1900G/GS)
(DB1200G/GS)
(DB1900G/GS)
9EX21501
9EX21501
IDT
®
15 Output PCIe G2/QPI Differential Buffer with 2:1 Input Mux 1578—01/18/11
9EX21501
15 Output PCIe G2/QPI Differential Buffer with 2:1 Input Mux
12
Datasheet
SMBusTable: Output, and PLL BW Control Register
Pin # Name Control Function T
yp
e0 1Default
Bit 7
RW Latch
Bit 6
RW Latch
Bit 5
1
Bit 4
DIF_14 Output Control RW Hi-Z Enable 1
Bit 3
0
Bit 2
100M_133M# Frequency Select Bit C RW 133MHz 100MHz Latch
Bit 1
FSB Frequenc
y
Select Bit B R
W
0
Bit 0
FSA Frequency Select bit A RW 1
SMBusTable: Output Control Register
Pin # Name Control Function T
yp
e0 1Default
Bit 7
1
Bit 6
DIF_6 Output Control R
W
Hi-Z Enable 1
Bit 5
DIF_5 Output Control RW Hi-Z Enable 1
Bit 4
DIF_4 Output Control RW Hi-Z Enable 1
Bit 3
DIF_3 Output Control RW Hi-Z Enable 1
Bit 2
DIF_2 Output Control R
W
Hi-Z Enable 1
Bit 1
DIF_1 Output Control RW Hi-Z Enable 1
Bit 0
DIF_0 Output Control RW Hi-Z Enable 1
SMBusTable: Output Control Register
Pin # Name Control Function Type 0 1 Default
Bit 7
DIF_13 Output Control RW Hi-Z Enable 1
Bit 6
1
Bit 5
DIF_12 Output Control RW Hi-Z Enable 1
Bit 4
DIF_11 Output Control R
W
Hi-Z Enable 1
Bit 3
DIF_10 Output Control RW Hi-Z Enable 1
Bit 2
DIF_9 Output Control RW Hi-Z Enable 1
Bit 1
DIF_8 Output Control RW Hi-Z Enable 1
Bit 0
DIF_7 Output Control RW Hi-Z Enable 1
SMBusTable: Output Enable Readback Register
Pin # Name Control Function T
yp
e0 1Default
Bit 7
OE10# Input Pin Readback
R
Pin Low Pin Hi X
Bit 6
OE9# Input Pin Readback
R
Pin Low Pin Hi X
Bit 5
OE8# Input Pin Readback
R
Pin Low Pin Hi X
Bit 4
OE7# Input Pin Readback
R
Pin Low Pin Hi X
Bit 3
1
Bit 2
OE6# Input Pin Readback
R
Pin Low Pin Hi X
Bit 1
OE5# Input Pin Readback
R
Pin Low Pin Hi X
Bit 0
OE_01234# Input Pin Readback
R
Pin Low Pin Hi X
RESERVED
RESERVED
RESERVED
RESERVED
00 = Low BW (1MHz)
10 = Bypass
11 = High BW (3MHz)
See Frequency Select
Table
B
y
te 3
63
30
46
43
50
1
4
PLL_BW# adjust
BYPASS# test mode / PLL
-
54
-
-
B
y
te 1
B
y
te 2
B
y
te 0
RESERVED
P1-P3P4-P6P7-P9P10-P12P13-P15

9EX21501AKILFT

Mfr. #:
Buy 9EX21501AKILFT
Manufacturer:
IDT
Description:
Clock Buffer PCIE BUFFER - GEN2. 15 OUTPUTS w/2:1 INP
Lifecycle:
New from this manufacturer.
Delivery:
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