OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

9EX21501AKILFT

P1-P3P4-P6P7-P9P10-P12P13-P15
IDT
®
15 Output PCIe G2/QPI Differential Buffer with 2:1 Input Mux 1578—01/18/11
9EX21501
15 Output PCIe G2/QPI Differential Buffer with 2:1 Input Mux
4
Datasheet
Pin Description (continued)
41 DIF_4 OUT 0.7V differential true clock output
42 DIF_4# OUT 0.7V differential complement clock output
43 OE5# IN
Active low input for enabling DIF pair 5.
1 = tri-state outputs, 0 = enable outputs
44 DIF_5 OUT 0.7V differential true clock output
45 DIF_5# OUT 0.7V differential complement clock output
46 OE6# IN
Active low input for enabling DIF pair 6.
1 = tri-state outputs, 0 = enable outputs
47 DIF_6 OUT 0.7V differential true clock output
48 DIF_6# OUT 0.7V differential complement clock output
49 VDD PWR Power supply, nominal 3.3V
50 OE7# IN
Active low input for enabling DIF pair 7.
1 = tri-state outputs, 0 = enable outputs
51 DIF_7 OUT 0.7V differential true clock output
52 DIF_7# OUT 0.7V differential complement clock output
53 100M_133M# IN Input to select operating frequency. See Frequency/Functionality Table for functionality of this pin.
54 HIBW_BYPM_LOBW# IN
Trilevel input to select High BW, Bypass Mode or Low BW.
0 = Low BW Mode, Mid= Bypass Mode, 1 = High Bandwidth
55 SMBCLK IN Clock pin of SMBUS circuitry, 5V tolerant
56 SMBDAT I/O Data pin of SMBUS circuitry, 5V tolerant
57 SMB_A1 IN SMBus address bit 1
58 SMB_A0 IN SMBus address bit 0 (LSB)
59 SEL_A_B# IN
Input to select differential input clock A or differential input clock B.
0 = Input B selected, 1 = Input A selected.
60 CKPWRGD/PD# IN Notifies the clock to sample latched inputs on the rising edge, and to power down on the falling edge.
61 DIF_8 OUT 0.7V differential true clock output
62 DIF_8# OUT 0.7V differential complement clock output
63 OE8# IN
Active low input for enabling DIF pair 8.
1 = tri-state outputs, 0 = enable outputs
64 VDD PWR Power supply, nominal 3.3V
IDT
®
15 Output PCIe G2/QPI Differential Buffer with 2:1 Input Mux 1578—01/18/11
9EX21501
15 Output PCIe G2/QPI Differential Buffer with 2:1 Input Mux
5
Datasheet
Electrical Characteristics - Absolute Maximum Ratings
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
3.3V Core Supply Voltage VDDA 4.6 V 1,2
3.3V Logic Supply Voltage VDD 4.6 V 1,2
Input Low Voltage V
IL
GND-0.5 V 1
Input High Voltage V
IH
Except for SMBus interface V
D
D
+0.5V V 1
Input High Voltage V
IHSMB
SMBus clock and data pins 5.5V V 1
Storage Temperature Ts -65 150
°
C
1
Junction Temperature Tj 125 °C 1
Input ESD protection
ESD prot Human Body Model 2000 V 1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Operation under these conditions is neither implied nor guaranteed.
Electrical Characteristics - Clock Input Parameters
TA = T
COM
or T
IND;
Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Input High Voltage - DIF_IN V
IHDIF
Differential inputs
(sin
g
le-ended measurement)
600 800 1150 mV 1
Input Low Voltage - DIF_IN V
ILDIF
Differential inputs
(single-ended measurement)
V
SS
- 300 0 300 mV 1
Input Common Mode
Voltage - DIF_IN
V
COM
Common Mode Input Voltage 300 400 1000 mV 1
Input Amplitude - DIF_IN V
SWING
Peak to Peak value 300 750 1450 mV 1
Input Slew Rate - DIF_IN dv/dt Measured differentially 0.4 2 8 V/ns 1,2
Input Leakage Current I
IN
V
IN
= V
DD ,
V
IN
=
GND -5 5 uA 1
Input Duty Cycle d
tin
Measurement from differential wavefrom 45 50 55 % 1
Input Jitter - Cycle to Cycle J
DIFI n
Differential Measurement 0 50 125 ps 1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Slew rate measured through +/-75mV window centered around differential zero
Electrical Characteristics - Phase Jitter Parameters
TA = T
COM
or T
IND;
Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes
t
jphPCIeG1
PCIe Gen 1 32/42 86
ps
(p-p)
1,2,3,4
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
1.2/1.5 3
ps
(rms)
1,2,4
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
2.1/2.7
3.1
ps
(rms)
1,2,4
t
jphQPI
QPI
(133MHz, 4.8Gb/s, 6.4Gb/s 12UI)
0.25/0.28 0.5
ps
(rms)
1,4,5
t
jphPCIeG1
PCIe Gen 1 2 10
ps
(p-p)
1,2,3
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
0.0 0.3
ps
(rms)
1,2,6
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
0.30 0.5
ps
(rms)
1,2,6
t
jphQPI
QPI
(133MHz, 4.8Gb/s, 6.4Gb/s 12UI)
0.25 0.4
ps
(rms)
1,5,6
1
Applies to all outputs. Device driven by IDT CK410B+ (932S421CGLF) or equivalent
6
For RMS figures, additive jitter is calculated by solving the following equation: (Additive jitter)^2 = (total jittter)^2 - (input jitter)^2
4
First number is Low BW
,
second number is Hi BW.
5
Calculated from Intel-su
pp
lied Clock Jitter Tool v 1.6.4
,
with 7.8M rolloff
Phase Jitter, PLL Mode
Additive Phase Jitter,
Bypass mode
t
jphPCIeG2
t
jphPCIeG2
2
See htt
://www.
cisi
.com for com
lete s
ecs
3
Sam
p
le size of at least 100K c
y
cles. This fi
g
ures extra
p
olates to 108
p
s
p
k-
p
k @ 1M c
y
cles for a BER of 1-12.
IDT
®
15 Output PCIe G2/QPI Differential Buffer with 2:1 Input Mux 1578—01/18/11
9EX21501
15 Output PCIe G2/QPI Differential Buffer with 2:1 Input Mux
6
Datasheet
Electrical Characteristics - Input/Supply/Common Parameters
TA = T
COM
or T
IND;
Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
T
COM
Commmercial range 0 25 70 °C 1
T
IND
Industrial range -40 25 85 °C 1
Input High Voltage V
IH
Single-ended inputs, except SMBus,
low threshold and tri-level inputs
2 2.400 V
DD
+ 0.3 V 1
Input Low Voltage V
IL
Single-ended inputs, except SMBus,
low threshold and tri-level inputs
GND
- 0.3 0.400 0.8 V 1
I
IN
Single-ended inputs, V
IN
= GND, V
IN
=
VDD
-5 5 uA 1
I
INP
Single-ended inputs
V
IN
= 0 V; Inputs with internal pull-up
resistors
V
IN
= VDD; Inputs with internal pull-
down resistors
-200 200 uA 1
F
ib
yp
V
DD
= 3.3 V, Bypass mode 33 400 MHz 2
F
i
p
ll
V
DD
= 3.3 V, 100MHz PLL mode 80 100.00 110 MHz 2
F
i
p
ll
V
DD
= 3.3 V, 133.33MHz PLL mode 120 133.33 150 MHz 2
Pin Inductance L
p
in
7nH1
C
IN
Logic Inputs, except DIF_IN 1.5 5 pF 1
C
INDIF_IN
DIF_IN differential clock inputs 1.5 2.7 pF 1,4
C
OUT
Output pin capacitance 6 pF 1
Clk Stabilization T
STAB
From V
DD
Power-Up and after input
clock stabilization or de-assertion of
PD# to 1st clock
0.5 1 ms 1,2
Input SS Modulation
Frequency
f
MODIN
Allowable Frequency
(Triangular Modulation)
30 33 kHz 1
OE# Latency t
LATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
4 10 12 clocks 1,3
Tdrive_PD# t
DRVPD
DIF output enable after
PD# de-assertion
0.2 300 us 1,3
Tfall t
F
Fall time of control inputs 5 ns 1,2
Trise t
R
Rise time of control inputs 5 ns 1,2
SMBus Input Low Voltage V
ILSMB
0.4 0.8 V 1
SMBus Input High Voltage V
IHSMB
2.1 2.4 V
DDSMB
V1
SMBus Output Low Voltage V
OLSMB
@ I
PULLUP
0.3 0.4 V 1
SMBus Sink Current I
PULLUP
@ V
OL
45 mA1
Nominal Bus Voltage V
DDSMB
3V to 5V +/- 10% 2.7 3.3 5.5 V 1
SCLK/SDATA Rise Time t
RSMB
(Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1
SCLK/SDATA Fall Time t
FSMB
(Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1
SMBus Operating
Frequency
f
MAXSMB
Maximum SMBus operating frequency 400 100 kHz 1,5
1
Guaranteed by desi
g
n and characterization, not 100% tested in production.
2
Control input must be monotonic from 20% to 80% of input swin
g
.
4
DIF_IN input
5
The differential in
p
ut clock must be runnin
g
for the SMBus to be active. Tested at Fin=100MHz.
3
Time from deassertion until out
p
uts are >200 mV
Input Current
Input Frequency
Capacitance
Ambient Operating
Temperature
P1-P3P4-P6P7-P9P10-P12P13-P15

9EX21501AKILFT

Mfr. #:
Buy 9EX21501AKILFT
Manufacturer:
IDT
Description:
Clock Buffer PCIE BUFFER - GEN2. 15 OUTPUTS w/2:1 INP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet