ICS9EX21501AKLF Datasheet 9EX21501AKILFT, 9EX21501AKLF, ICS9EX21501AKILF | P1-P3

9EX21501A

IDT

15 Output PCIe G2/QPI Differential Buffer with 2:1 Input Mux 1578—07/18/11

15 Output PCIe G2/QPI Differential Buffer with

2:1 Input Mux

DATASHEET

Functional Block Diagram

Description

The ICS9EX21501 provides 15 output clocks for PCIe Gen2

(100MHz) or QPI (133MHz) applications. A differential CPU clock

from a CK410B+ main clock generator, such as the ICS932S421,

drives the ICS9EX21501. In fanout mode, the ICS9EX21501

provides outputs up to 400MHz. A 2:1 input mux allows selection

between local and remote clock sources.

Recommended Application:

15 Output PCIe G2/QPI Differential Buffer with 2:1 input mux

Key Specifications:

• DIF output cycle-to-cycle jitter < 50ps

• DIF output-to-output skew < 150 ps

• PCIe Gen2 compliant phase jitter

• QPI 6.4Gb/s 12UI compliant phase jitter

Features/Benefits:

• Output clock frequencies up to 400 MHz/supports wide

range of applications

• 4 Selectable SMBus addresses/multiple devices can share

SMBus segment

• SMBus address independent of PLL operating mode/

maximum flexibility

• Dedicated CKPWRGD/PD# and VDDA pins/Easy board

design

• 8 Dedicated OE# and 2 Group OE# pins/Support for

hardware clock management

Output Features:

• 15 - 0.7V current-mode differential HCSL output pairs

• Supports zero delay buffer mode and fanout mode

• Selectable PLL bandwidth

• 80-150 MHz in PLL Mode

• 33-400 MHz operation in Bypass mode

CLKA_IN

CLKA_IN#

DIF(14:0)

HIBW_BYPM_LOBW#

SEL_A_B#

SMBDAT

SMBCLK

CKPWRGD/PD#

IREF

OE13_14#

OE(5:12)#,

OE_01234#

SMB_A0

SMB_A1

100M_133M#

CLKB_IN

CLKB_IN#

PLL

(SS Compatible)

Logic

IDT

15 Output PCIe G2/QPI Differential Buffer with 2:1 Input Mux 1578—01/18/11

9EX21501

15 Output PCIe G2/QPI Differential Buffer with 2:1 Input Mux

Datasheet

PIn Configuration

VDD

OE8#

DIF_8#

DIF_8

CKPWRGD/PD#

SEL_A_B#

SMB_A0

SMB_A1

SMBDAT

SMBCLK

HIBW_BYPM_LOBW#

100M_133M#

DIF_7#

DIF_7

OE7#

VDD

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

OE9# 1 48 DIF_6#

DIF_9 2 47 DIF_6

DIF_9# 3 46 OE6#

OE10# 4 45 DIF_5#

DIF_10 5 44 DIF_5

DIF_10# 6 43 OE5#

OE11# 7 42 DIF_4#

DIF_11 8 41 DIF_4

DIF_11# 9 40 DIF_3#

GND 10 39 DIF_3

VDD 11 38 GND

DIF_12 12 37 VDD

DIF_12# 13 36 DIF_2#

OE12# 14 35 DIF_2

DIF_13 15 34 DIF_1#

DIF_13# 16 33 DIF_1

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

VDD

OE13_14#

DIF_14

DIF_14#

IREF

GNDA

VDDA

CLKA_IN

CLKA_IN#

GND

CLKB_IN

CLKB_IN#

VDD

OE_01234#

DIF_0

DIF_0#

9EX21501

64-pin MLF

Byte 0,

bit 2

(100_133M#

Latch

)

Byte 0,

bit 1

FSB

Byte 0,

bit 0

FSA

Input

MHz

DIF_x

MHz

Notes

100.00 100.00

133.33 133.33

011

166.67 166.67 2

010

200.00 200.00 2

000

266.67 266.67 2

100

333.33 333.33 2

110

400.00 400.00 2

111

Notes:100M_133M#

1. Latch selects between 100 and 133 MHz.

This is equivalent to FSC in CK410B+/CK509B FS table.

2. Writing Byte 2 bits (2:0) can select other frequencies.

These frequencies are not characterized in PLL Mode

Frequency/Functionality Table

Reserved

HIBW_BYPM_LOBW# Selection (Pin 54)

State Voltage Mode

Low <0.8V Low BW

Mid 1.2<Vin<1.8V Bypass

High Vin > 2.0V High BW

SMBus Address Selection (pins 57, 58)

SMB_A1 SMB_A0 Address

00D4

01D6

10D8

11DA

Power Groups

Power Down Functionality

OUTPUTS

CKPWRGD/PD# In

ut DIF_x

1 Runnin

Runnin

0XHi-ZOFF

PLL State

INPUTS

VDD GND

23 22 Main PLL, Analog

29 26 Input buffers

11,17,37,49, 64 10, 38 DIF clocks

Description

Pin Number

IDT

15 Output PCIe G2/QPI Differential Buffer with 2:1 Input Mux 1578—01/18/11

9EX21501

15 Output PCIe G2/QPI Differential Buffer with 2:1 Input Mux

Datasheet

Pin Description

PIN # PIN NAME TYPE DESCRIPTION

1OE9# IN

Active low input for enabling DIF pair 9.

1 = tri-state outputs, 0 = enable outputs

2 DIF_9 OUT 0.7V differential true clock output

DIF_9# OUT 0.7V differential complement clock output

4 OE10# IN

Active low input for enabling DIF pair 10.

1 = tri-state outputs, 0 = enable outputs

5 DIF_10 OUT 0.7V differential true clock output

6 DIF_10# OUT 0.7V differential complement clock output

7 OE11# IN

Active low input for enabling DIF pair 11.

1 = tri-state outputs, 0 = enable outputs

8 DIF_11 OUT 0.7V differential true clock output

9 DIF_11# OUT 0.7V differential complement clock output

10 GND PWR Ground pin.

11 VDD PWR Power supply, nominal 3.3V

12 DIF_12 OUT 0.7V differential true clock output

13 DIF_12# OUT 0.7V differential complement clock output

14 OE12# IN

Active low input for enabling DIF pair 12.

1 = tri-state outputs, 0 = enable outputs

15 DIF_13 OUT 0.7V differential true clock output

16 DIF_13# OUT 0.7V differential complement clock output

17 VDD PWR Power supply, nominal 3.3V

18 OE13_14# IN

Active low input for enabling DIF pairs 13 and 14

1 = tri-state outputs, 0 = enable outputs

19 DIF_14 OUT 0.7V differential true clock output

20 DIF_14# OUT 0.7V differential complement clock output

21 IREF OUT

This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed

precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value.

22 GNDA PWR Ground pin for the PLL core.

23 VDDA PWR 3.3V power for the PLL core.

24 CLKA_IN IN True Input for differential reference clock.

25 CLKA_IN# IN Complement Input for differential reference clock.

26 GND PWR Ground pin.

27 CLKB_IN IN True Input for differential reference clock.

28 CLKB_IN# IN Complement Input for differential reference clock.

29 VDD PWR Power supply, nominal 3.3V

30 OE_01234# IN

Active low input for enabling DIF pairs 0, 1, 2, 3 and 4.

1 = tri-state outputs, 0 = enable outputs

31 DIF_0 OUT 0.7V differential true clock output

32 DIF_0# OUT 0.7V differential complement clock output

33 DIF_1 OUT 0.7V differential true clock output

34 DIF_1# OUT 0.7V differential complement clock output

35 DIF_2 OUT 0.7V differential true clock output

36 DIF_2# OUT 0.7V differential complement clock output

37 VDD PWR Power supply, nominal 3.3V

38 GND PWR Ground pin.

39 DIF_3 OUT 0.7V differential true clock output

40 DIF_3# OUT 0.7V differential complement clock output

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15

ICS9EX21501AKLF

Mfr. #:

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IC FANOUT/BUFFER DIFF 64QFPN

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ICS9EX21501AKLF

ICS9EX21501AKLF

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