SC16C850L All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 6 — 11 October 2013 4 of 55
NXP Semiconductors
SC16C850L
1.8 V single UART with 128-bute FIFOs and IrDA encoder/decoder
Fig 2. Block diagram of SC16C850L (68 mode)
TX
RX
SC16C850L
XTAL2XTAL1
D0 to D7
R/W
RESET
002aac417
DATA BUS
AND
CONTROL
LOGIC
REGISTER
SELECT
LOGIC
A0 to A2
CS
INTERRUPT
CONTROL
LOGIC
IRQ
CLOCK AND
BAUD RATE
GENERATOR
INTERCONNECT BUS LINES
AND
CONTROL SIGNALS
MODEM
CONTROL
LOGIC
DTR
RTS
CTS
RI
CD
DSR
RECEIVE
SHIFT
REGISTER
RECEIVE
FIFO
REGISTER
FLOW
CONTROL
LOGIC
FLOW
CONTROL
LOGIC
TRANSMIT
SHIFT
REGISTER
TRANSMIT
FIFO
REGISTER
IR
DECODER
IR
ENCODER
POWER-DOWN
CONTROL
LOWPWR
SC16C850L All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 6 — 11 October 2013 5 of 55
NXP Semiconductors
SC16C850L
1.8 V single UART with 128-bute FIFOs and IrDA encoder/decoder
5. Pinning information
5.1 Pinning
Fig 3. Pin configuration for TFBGA36
Transparent top view.
Fig 4. Ball mapping for TFBGA36
002aac418
SC16C850LIET
Transparent top view
F
E
D
C
A
B
246135
ball A1
index area
V
DD
n.c. n.c. XTAL2
12345
A2 n.c. n.c. IOW LOWPWR
A
B
A0 V
SS
A1 V
SS
TXC
INT CTS V
DD
D7D
DTR n.c. CD D1 D3E
RESET DSR D0 D2F
RTS
RI
002aac421
XTAL1
6
CS
RX
D6
D5
D4
IOR
SC16C850L All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 6 — 11 October 2013 6 of 55
NXP Semiconductors
SC16C850L
1.8 V single UART with 128-bute FIFOs and IrDA encoder/decoder
5.2 Pin description
a. 16 mode b. 68 mode
Fig 5. Pin configuration for HVQFN32
002aac419
SC16C850LIBS
(16 mode)
Transparent top view
A2
TX
CS
A1
RX A0
D7 INT
D6
D5 DTR
16
D4 CTS
LOWPWR
XTAL1
XTAL2
IOW
V
SS
IOR
n.c.
n.c.
D3
D2
D1
D0
V
DD
RI
CD
DSR
8 17
7 18
6 19
5 20
4 21
3 22
2 23
1 24
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
terminal 1
index area
RTS
RESET
002aac631
SC16C850LIBS
(68 mode)
Transparent top view
A2
TX
CS
A1
RX A0
D7 IRQ
D6
D5 DTR
68
D4 CTS
LOWPWR
XTAL1
XTAL2
R/W
V
SS
V
DD
n.c.
n.c.
D3
D2
D1
D0
V
DD
RI
CD
DSR
8 17
7 18
6 19
5 20
4 21
3 22
2 23
1 24
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
terminal 1
index area
RTS
RESET
Table 2. Pin description
Symbol Pin Type Description
TFBGA36 HVQFN32
16/68
-2IBus select. Intel or Motorola bus select.
When 16/68
pin is at logic 1 or left unconnected (internally pulled-up) the
device will operate in Intel bus (16 mode) type of interface.
When 16/68 pin is at logic 0, the device will operate in Motorola bus (68 mode)
type of interface.
A0 C1 19 I Address 0 select bit. Internal register address selection.
A1 C3 18 I Address 1 select bit. Internal register address selection.
A2 B1 17 I Address 2 select bit. Internal register address selection.
CD
E3 26 I Carrier Detect (active LOW). A logic 0 on this pin indicates that a carrier has
been detected by the modem. Status can be tested by reading MSR[7].
CS
B6 8 I Chip Select (active LOW). In 16 mode or 68 mode, this input is chip select for
the UART.
CTS
D3 24 I Clear to Send (active LOW). A logic 0 on the CTS pin indicates the modem
or data set is ready to accept transmit data from the SC16C850L. Status can
be tested by reading MSR[4].
DSR
F2 25 I Data Set Ready (active LOW). A logic 0 on this pin indicates the modem or
data set is powered-on and is ready for data exchange with the UART. Status
can be tested by reading MSR[5].
DTR
E1 22 O Data Terminal Ready (active LOW). A logic 0 on this pin indicates that the
SC16C850L is powered-on and ready. This pin can be controlled via the
modem control register. Writing a logic 1 to MCR[0] will set the DTR
output to
logic 0, enabling the modem. This pin will be a logic 1 after writing a logic 0 to
MCR[0], or after a reset.

SC16C850LIBS,157

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC UART SINGLE W/FIFO 32-HVQFN
Lifecycle:
New from this manufacturer.
Delivery:
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