SC16C850LIBS,157 Datasheet SC16C850LIET,115, SC16C850LIBS,115, SC16C850LIBS,128 | P7-P9

Product data sheet Rev. 6 — 11 October 2013 7 of 55

NXP Semiconductors

SC16C850L

1.8 V single UART with 128-bute FIFOs and IrDA encoder/decoder

D0 F4 29 I/O Data bus (bidirectional). These pins are the 8-bit, 3-state data bus for

transferring information to or from the controlling CPU. D0 is the least

significant bit and the first data bit in a transmit or receive serial data stream.

D1 E4 30 I/O

D2 F5 31 I/O

D3 E5 32 I/O

D4 F6 1 I/O

D5 E6 3 I/O

D6 D6 4 I/O

D7 D5 5 I/O

INT

(IRQ

)

- 20 O When 16/68 pin is at logic 1 or unconnected, this output becomes active HIGH

interrupt output. The output state is defined by the user through the software

setting of MCR[5]. INT is set to the active mode when MCR[5] is set to a

logic 1. INT is set to the open-source mode when MCR[5] is set to a logic 0.

When 16/68

pin is at logic 0, this output becomes device interrupt output

(active LOW, open-drain). An external pull-up resistor to V

is required.

INT D1 - O Interrupt output (active HIGH). The output state is defined by the user

through the software setting of MCR[5]. INT is set to the active mode when

MCR[5] is set to a logic 1. INT is set to the open-source mode when MCR[5] is

set to a logic 0.

IOR

)

-14IWhen 16/68 pin is at logic 1, this input becomes the read strobe (active LOW).

When 16/68

pin is at logic 0, this input pin is not used and should be

connected to V

IOR

A3 - I Read strobe (active LOW).

IOW

(R/W)

- 12 I When 16/68

pin is at logic 1 or unconnected, this input becomes the write

strobe (active LOW).

When 16/68 pin is at logic 0, this input becomes read strobe when it is at logic

HIGH, and write strobe when it is at logic LOW.

IOW

B4 - I Write strobe (active LOW).

LOWPWR B5 9 I Low Power. When asserted (active HIGH), the device immediately goes into

low power mode. The oscillator is shut-off and some host interface pins are

isolated from the host’s bus to reduce power consumption. The device only

returns to normal mode when the LOWPWR pin is de-asserted. On the

negative edge of a de-asserting LOWPWR signal, the device is automatically

reset and all registers return to their default reset states. This pin has a 22 k

internal pull-down resistor, therefore, it can be left unconnected (refer to

Section 6.12 “

Low power feature”).

RESET

(RESET

)

-23IMaster Reset. When 16/68 pin is at logic 1 or unconnected, this input

becomes the RESET pin (active HIGH).

When 16/68 pin is at logic LOW, this input pin becomes RESET (active LOW).

(See Section 7.23 “SC16C850L external reset condition and software reset”

for initialization details.)

RESET F1 - I Reset input (active HIGH). See Section 7.23 “

SC16C850L external reset

condition and software reset” for initialization details.

F3 27 I Ring Indicator (active LOW). A logic 0 on this pin indicates the modem has

received a ringing signal from the telephone line. A logic 1 transition on this

input pin will generate an interrupt if modem status interrupt is enabled. Status

can be tested by reading MCR[6].

Table 2. Pin description

…continued

Symbol Pin Type Description

TFBGA36 HVQFN32

Product data sheet Rev. 6 — 11 October 2013 8 of 55

NXP Semiconductors

SC16C850L

1.8 V single UART with 128-bute FIFOs and IrDA encoder/decoder

[1] HVQFN package die supply ground is connected to both V

pin and exposed center pad. V

pin must be connected to supply ground

for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to

the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be

incorporated in the PCB in the thermal pad region.

RTS D2 21 O Request to Send (active LOW). A logic 0 on the RTS pin indicates the

transmitter has data ready and waiting to send. Writing a logic 1 in the modem

control register MCR[1] will set this pin to a logic 0, indicating data is available.

After a reset this pin will be set to a logic 1.

RX C6 6 I UART receive data. The RX signal will be a logic 1 during reset, idle (no

data), or when not receiving data. During the local loopback mode, the RX

input pin is disabled and TX data is connected to the UART RX input,

internally.

TX C5 7 O UART transmit data. The TX signal will be a logic 1 during reset, idle (no

data), or when the transmitter is disabled. During the local loopback mode, the

TX output pin is disabled and TX data is internally connected to the UART RX

input.

A1, D4 28 I Power supply input.

C2, C4 13

[1]

I Signal and power ground.

XTAL1 A6 10 I Crystal or external clock input. Functions as a crystal input or as an external

clock input. A crystal can be connected between this pin and XTAL2 to form an

internal oscillator circuit. Alternatively, an external clock can be connected to

this pin to provide custom data rates (see Section 6.9 “

Programmable baud

rate generator”). See Figure 8.

XTAL2 A5 11 O Output of the crystal oscillator or buffered clock. Crystal oscillator output

or buffered clock output. Should be left open if an external clock is connected

to XTAL1.

Table 2. Pin description

…continued

Symbol Pin Type Description

TFBGA36 HVQFN32

Product data sheet Rev. 6 — 11 October 2013 9 of 55

NXP Semiconductors

SC16C850L

1.8 V single UART with 128-bute FIFOs and IrDA encoder/decoder

6. Functional description

The SC16C850L provides serial asynchronous receive data synchronization,

parallel-to-serial and serial-to-parallel data conversions for both the transmitter and

receiver sections. These functions are necessary for converting the serial data stream into

parallel data that is required with digital data systems. Synchronization for the serial data

stream is accomplished by adding start and stop bits to the transmit data to form a data

character (character orientated protocol). Data integrity is ensured by attaching a parity bit

to the data character. The parity bit is checked by the receiver for any transmission bit

errors. The electronic circuitry to provide all these functions is fairly complex, especially

when manufactured on a single integrated silicon chip. The SC16C850L represents such

an integration with greatly enhanced features. The SC16C850L is fabricated with an

advanced CMOS process.

The SC16C850L is an upward solution to the SC16C650B that provides a single UART

capability with 128 bytes of transmit and receive FIFO memory, instead of 32 bytes for the

16C650B and 16 bytes in the 16C550B. The SC16C850L is designed to work with high

speed modems and shared network environments that require fast data processing time.

Increased performance is realized in the SC16C850L by the transmit and receive FIFOs.

This allows the external processor to handle more networking tasks within a given time. In

addition, the four selectable receive and transmit FIFO trigger interrupt levels are provided

in 16C650 mode, or 128 programmable levels are provided in the extended mode for

maximum data throughput performance especially when operating in a multi-channel

environment (see Section 6.2 “

Extended mode (128-byte FIFO)”). The FIFO memory

greatly reduces the bandwidth requirement of the external controlling CPU and increases

performance. A low power pin (LOWPWR) is provided to further reduce power

consumption by isolating the host bus interface.

The SC16C850L is capable of operation up to 5 Mbit/s with an external 80 MHz clock.

With a crystal, the SC16C850L is capable of operation up to 1.5 Mbit/s.

The rich feature set of the SC16C850L is available through internal registers. These

features are: selectable and programmable receive and transmit FIFO trigger levels,

selectable TX and RX baud rates, and modem interface controls, and are all standard

features. Following a power-on reset, an external reset, or a software reset, the

SC16C850L is software compatible with the previous generation, SC16C550B, and

SC16C650B.

6.1 UART selection

The UART provides the user with the capability to bidirectionally transfer information

between an external CPU, the SC16C850L package, and an external serial device. A

logic 0 (LOW) on chip select pin CS

allows the user to configure, send data, and/or

receive data via the UART. Refer to Table 3

and Table 4.

Table 3. Serial port selection (Intel interface)

H = HIGH; L = LOW.

Chip Select Function

= H none

= L UART select

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P54 P55-P55

SC16C850LIBS,157

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Manufacturer:

NXP Semiconductors

Description:

IC UART SINGLE W/FIFO 32-HVQFN

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SC16C850LIBS,157

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