SC16C850L All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 6 — 11 October 2013 40 of 55
NXP Semiconductors
SC16C850L
1.8 V single UART with 128-bute FIFOs and IrDA encoder/decoder
[1] Applies to external clock, crystal oscillator max 24 MHz.
[2] Maximum frequency =
[3] RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches.
Table 38. Dynamic characteristics - Motorola or 68 mode
T
amb
=
40
C to +85
C; V
DD
= 1.65 V to 1.95 V; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
t
WH
pulse width HIGH 6 - - ns
t
WL
pulse width LOW 6 - - ns
t
w(clk)
clock pulse width 12.5 - - ns
f
XTAL1
frequency on pin XTAL1
[1][2]
--80MHz
t
su(A)
address set-up time 5 - - ns
t
h(A)
address hold time 10 - - ns
t
su(RWL-CSL)
set-up time from R/W LOW to CS LOW 10--ns
t
su(RWH-CSL)
set-up time from R/W HIGH to CS LOW 10--ns
t
w(CS)
CS pulse width 25 pF load 20 - - ns
t
d(CS)
CS delay time 25 pF load 10 - - ns
t
d(CS-Q)
delay time from CS to data output 25 pF load - - 40 ns
t
dis(CS-QZ)
disable time from CS to high-impedance
data output
25 pF load - - 20 ns
t
h(CS-RWH)
hold time from CS to R/W HIGH 5 - - ns
t
d(RW)
R/W delay time 10--ns
t
su(D-CSH)
set-up time from data input to CS HIGH 5--ns
t
h(CSH-D)
data input hold time after CS HIGH 5 - - ns
t
d(modem-IRQL)
delay time from modem to IRQ LOW --50ns
t
d(CS-IRQH)R
read delay time from CS to IRQ HIGH - - 50 ns
t
d(stop-IRQL)
delay time from stop to IRQ LOW
[3]
--1T
RCLK
s
t
d(CS-TX)W
write delay time from CS to TX
[3]
8T
RCLK
-24T
RCLK
s
t
d(start-IRQL)
delay time from start to IRQ LOW
[3]
--1T
RCLK
s
t
d(CS-IRQH)W
write delay time from CS to IRQ HIGH --50ns
t
d(CS-Q)W
write delay time from CS to data output - - 50 ns
t
w(RESET_N)
pulse width on pin RESET 10--ns
N baud rate divisor 1 - (2
16
1)
1
t
wclk
---------------
