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SC16C850LIET,157

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P55
SC16C850L All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 6 — 11 October 2013 43 of 55
NXP Semiconductors
SC16C850L
1.8 V single UART with 128-bute FIFOs and IrDA encoder/decoder
Fig 15. Modem input/output timing (16 mode)
t
d(IOW-Q)
change of state
t
d(modem-INT)
t
d(IOR-INTL)
002aac409
change of state
change of state change of state
active
activ
e activ
e active
active active active
change of state
RTS
DTR
IOW
CD
CTS
DSR
INT
IOR
RI
t
d(modem-INT)
t
d(modem-INT)
(1) CS timing during a write cycle. See Figure 11.
(2) CS
timing during a read cycle. See Figure 13.
Fig 16. Modem input/output timing (68 mode)
t
d(CS-Q)W
change of state
t
d(modem-IRQL)
t
d(modem-IRQL)
t
d(CS-IRQH)R
002aac632
t
d(modem-IRQL)
change of state
change of state change of state
active
activ
e activ
e active
active active active
change of state
RTS
DTR
CS (wr
ite)
(1)
CD
CTS
DSR
IRQ
CS (read)
(2)
RI
SC16C850L All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 6 — 11 October 2013 44 of 55
NXP Semiconductors
SC16C850L
1.8 V single UART with 128-bute FIFOs and IrDA encoder/decoder
(1) INT is active when RX FIFO fills up to trigger level or a time-out condition happens (see Section 6.8).
(2) INT is cleared when RX FIFO drops below trigger level.
Fig 17. Receive timing in 16 mode
D0 D1 D2 D3 D4 D5 D6 D7
active
active
16 baud rate clock
002aac410
RX
INT
(1)(2)
IOR
t
d(IOR-INTL)
t
d(stop-INT)
5 data bits
6 data bits
7 data bits
stop
bit
parity
bit
start
bit
data bits (0 to 7)
next data
start
bit
(1) IRQ is active when RX FIFO fills up to trigger level or time-out condition happens (see Section 6.8).
(2) IRQ
is cleared when RX FIFO drops below trigger level.
Fig 18. Receive timing in 68 mode
D0 D1 D2 D3 D4 D5 D6 D7
active
active
16 baud rate clock
002aac633
t
d(CS-IRQH)R
next data
start
bit
stop
bit
parity
bit
start
bit
t
d(stop-IRQL)
RX
IRQ
(1)(2)
CS (read)
data bits (0 to 7)
5 data bits
6 data bits
7 data bits
SC16C850L All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 6 — 11 October 2013 45 of 55
NXP Semiconductors
SC16C850L
1.8 V single UART with 128-bute FIFOs and IrDA encoder/decoder
(1) INT is active when TX FIFO is empty or TX FIFO drops below trigger level.
(2) INT is cleared when ISR is read or TX FIFO fills up to trigger level.
Fig 19. Transmit timing in 16 mode
active
transmitter ready
active
16 baud rate clock
002aac413
t
d(IOW-INTL)
INT
(1)(2)
IOW
active
D0 D1 D2 D3 D4 D5 D6 D7
TX
5 data bits
6 data bits
7 data bits
stop
bit
parity
bit
start
bit
data bits (0 to 7)
next data
start
bit
t
d(start-INT)
t
d(IOW-TX)
(1) IRQ is active when TX FIFO is empty or TX FIFO drops below trigger level.
(2) IRQ
is cleared when ISR is read or TX FIFO fills up to trigger level.
Fig 20. Transmit timing in 68 mode
D0 D1 D2 D3 D4 D5 D6 D7
active
TX ready
active
16 baud rate clock
002aac634
t
d(CS-IRQH)W
start
bit
t
d(start-IRQL)
TX
IRQ
(1)(2)
CS (write)
data bits (0 to 7)
active
t
d(CS-TX)W
5 data bits
6 data bits
7 data bits
parity
bit
stop
bit
next data
start
bit
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P55

SC16C850LIET,157

Mfr. #:
Buy SC16C850LIET,157
Manufacturer:
NXP Semiconductors
Description:
IC UART SINGLE W/FIFO 36TFBGA
Lifecycle:
New from this manufacturer.
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