©2012 Integrated Device Technology, Inc.
JUNE 2012
DSC 2941/10
1
IDT70V05S/L
HIGH-SPEED 3.3V
8K x 8 DUAL-PORT
STATIC RAM
Features
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
Commercial: 15/20/25/35/55ns (max.)
Industrial: 20ns (max.)
Low-power operation
IDT70V05S
Active: 400mW (typ.)
Standby: 3.3mW (typ.)
IDT70V05L
Active: 380mW (typ.)
Standby: 660
µ
W (typ.)
IDT70V05 easily expands data bus width to 16 bits or more
using the Master/Slave select when cascading more than
one device
M/S = VIH for BUSY output flag on Master
M/S = V
IL for BUSY input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 3.3V (±0.3V) power supply
Available in 68-pin PGA and PLCC, and a 64-pin TQFP
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Functional Block Diagram
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY outputs and INT outputs are non-tri-stated push-pull.
I/O
Control
Address
Decoder
MEMORY
ARRAY
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
Address
Decoder
I/O
Control
R/W
L
CE
L
OE
L
BUSY
L
A
12L
A
0L
2942 drw 01
I/O
0L
-I/O
7L
CE
L
OE
L
R/W
L
SEM
L
INT
L
M/S
BUSY
R
I/O
0R
-I/O
7R
A
12R
A
0R
SEM
R
INT
R
CE
R
OE
R
(2)
(1,2) (1,2)
(2)
R/W
R
CE
R
OE
R
13
13
R/W
R
,
6.42
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
2
Description
The IDT70V05 is a high-speed 8K x 8 Dual-Port Static RAM. The
IDT70V05 is designed to be used as a stand-alone 64K-bit Dual-Port
SRAM or as a combination MASTER/SLAVE Dual-Port SRAM for 16-bit-
or-more word systems. Using the IDT MASTER/SLAVE Dual-Port SRAM
approach in 16-bit or wider memory system applications results in full-
speed, error-free operation without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by CE permits the on-chip circuitry of each port to enter
a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 400mW of power.
The IDT70V05 is packaged in a ceramic 68-pin PGA and PLCC
and a 64-pin thin quad flatpack (TQFP).
Pin Configurations
(1,2,3)
NOTES:
1. All V
CC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. J68-1 package body is approximately .95 in x .95 in x .17 in.
PN64 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate oriention of the actual part-marking
2941 drw 02
12
13
14
15
16
17
18
INDEX
19
20
21
22
987 6543 2168676665
27 28 29 30 31 32 33 34 35 36 37 38 39
V
D
D
V
DD
I/O
1R
I/O
2R
I/O
3R
I/O
4R
INT
L
V
SS
A
4L
A
3L
A
2L
A
1L
A
0L
A
3R
A
0R
A
1R
A
2R
I/O
2L
A
5L
R
/
W
L
11
10
M/S
23
24
25
26
40 41 42 43
58
57
56
55
54
53
52
51
50
49
48
59
60
47
46
45
44
64 63 62 61
I/O
3L
V
SS
I/O
0R
V
DD
A
4R
BUSY
L
V
SS
BUSY
R
INT
R
A
1
2
R
I
/
O
7
R
N
/
C
V
S
S
O
E
R
R
/
W
R
S
E
M
R
C
E
R
O
E
L
S
E
M
L
C
E
L
N
/
C
I
/
O
0
L
I
/
O
1
L
IDT70V05J
J68-1
(4)
68-Pin PLCC
Top View
(5)
I/O
4L
I/O
5L
I/O
6L
I/O
7L
I/O
5R
I/O
6R
N
/
C
A
1
2
L
A
1
1
R
N
/
C
A
1
0
R
A
9
R
A
8
R
A
7
R
A
6
R
A
5
R
A
1
1
L
A
1
0
L
A
9
L
A
8
L
A
7
L
A
6
L
N
/
C
N
/
C
,
12/03/01
INDEX
70V05PF
PN-64
(4)
64-Pin TQFP
Top View
(5)
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
46
45
44
43
42
41
40
39
38
37
36
35
34
47
48
33
1
7
1
8
1
9
2
0
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
4
9
5
0
5
1
5
2
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
6
4
I/O
2L
V
DD
V
SS
V
SS
A
4R
BUSY
L
BUSY
R
INT
R
INT
L
V
SS
M/S
O
E
L
A
5
L
I
/
O
1
L
R
/
W
L
C
E
L
S
E
M
L
V
D
D
N
/
C
N
/
C
O
E
R
C
E
R
R
/
W
R
S
E
M
R
A
1
2
R
G
N
D
I/O
3L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
I/O
0R
I/O
1R
I/O
2R
V
DD
I/O
3R
I/O
4R
I/O
5R
I
/
O
6
R
I
/
O
7
R
A
1
1
R
A
1
0
R
A
9
R
A
8
R
A
7
R
A
6
R
A
5
R
A
3R
A
2R
A
1R
A
0R
A
0L
A
1L
A
2L
A
3L
A
4L
A
6
L
A
7
L
A
8
L
A
9
L
A
1
0
L
A
1
1
L
A
1
2
L
I
/
O
0
L
2941 drw 03
,
12/03/01
6.42
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
3
NOTES:
1. All V
CC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 1.18 in x 1.18 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate oriention of the actual part-marking.
Pin Configurations
(1,2,3)
(con't.)
2941 drw 04
51 50 48 46 44 42 40 38 36
53
55
57
59
61
63
65
67
68
66
13579
11 13 15
20
22
24
26
28
30
32
35
IDT70V05G
G68-1
(4)
68-Pin PGA
Top View
(5)
ABCDEFGH JKL
47 45 43 41 34
21
23
25
27
29
31
33
246810121416
18 19
17
56
58
60
62
64
11
10
09
08
07
06
05
04
03
02
01
52
54
49 39 37
A
5L
INT
L
N/C
SEM
L
CE
L
V
DD
OE
L
R/W
L
I/O
0L
N/C
V
SS
V
SS
I/O
0R
V
DD
N/C
OE
R
R/W
R
SEM
R
CE
R
V
SS
BUSY
R
BUSY
L
M/S
INT
R
N/C
V
SS
A
1R
N/C
N/C
INDEX
A
4L
A
2L
A
0L
A
3R
A
2R
A
4R
A
5R
A
7R
A
6R
A
9R
A
8R
A
11R
A
10R
A
12R
A
0R
A
7L
A
6L
A
3L
A
1L
A
9L
A
8L
A
11L
A
10L
A
12L
V
DD
I/O
2R
I/O
3R
I/O
5R
I/O
6R
I/O
1R
I/O
4R
I/O
7R
I/O
1L
I/O
2L
I/O
4L
I/O
7L
I/O
3L
I/O
5L
I/O
6L
12
/
03
/
01
Pin Names
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EC
L
EC
R
elbanEpihC
/R W
L
/R W
R
elbanEetirW/daeR
EO
L
EO
R
elbanEtuptuO
A
0
L
A-
21
L
A
0
R
A-
21
R
sserddA
O/I
0
L
O/I-
7
L
O/I
0
R
O/I-
7
R
tuptuO/tupnIataD
MES
L
MES
R
elbanEerohpameS
TNI
L
TNI
R
galFtpurretnI
YSUB
L
YSUB
R
galFysuB
/M S tceleSevalSroretsaM
V
DD
)v3.3(rewoP
V
SS
)v0(dnuorG
00lbt1492

70V05L15JG

Mfr. #:
Manufacturer:
IDT
Description:
SRAM 8K x 8 3.3v Dual- Port Ram
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union