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70V05L15JG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
6.42
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
10
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is determined by device characterization but is not production tested.
3. To access SRAM, CE = V
IL, SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for t
DH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and
temperature, the actual t
DH will always be smaller than the actual tOW.
5. “X” in part number indicates power rating (S or L).
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage
(5)
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02X50V07
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52X50V07
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ELCYCETIRW
t
CW
emiTelcyCetirW51
____
02
____
52
____
sn
t
WE
etirW-fo-dnEotelbanEpihC
)3(
21
____
51
____
02
____
sn
t
WA
etirW-fo-dnEotdilaVsserddA21
____
51
____
02
____
sn
t
SA
emiTpu-teSsserddA
)3(
0
____
0
____
0
____
sn
t
PW
htdiWesluPetirW21
____
51
____
02
____
sn
t
RW
emiTyrevoceRetirW0
____
0
____
0
____
sn
t
WD
etirW-fo-dnEotdilaVataD01
____
51
____
51
____
sn
t
ZH
emiTZ-hgiHtuptuO
)2,1(
____
01
____
21
____
51sn
t
HD
emiTdloHataD
)4(
0
____
0
____
0
____
sn
t
ZW
Z-hgiHnituptuOotelbanEetirW
)2,1(
____
01
____
21
____
51sn
t
WO
etirW-fo-dnEmorfevitcAtuptuO
)4,2,1(
0
____
0
____
0
____
sn
t
DRWS
MES emiTdaeRotetirWgalF
5
____
5
____
5
____
sn
t
SPS
MES wodniWnoitnetnoCgalF
5
____
5
____
5
____
sn
a21lbt1492
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55X50V07
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ELCYCETIRW
t
CW
emiTelcyCetirW 53
____
55
____
sn
t
WE
etirW-fo-dnEotelbanEpihC
)3(
03
____
54
____
sn
t
WA
etirW-fo-dnEotdilaVsserddA 03
____
54
____
sn
t
SA
emiTpu-teSsserddA
)3(
0
____
0
____
sn
t
PW
htdiWesluPetirW 52
____
04
____
sn
t
RW
emiTyrevoceRetirW 0
____
0
____
sn
t
WD
etirW-fo-dnEotdilaVataD 51
____
03
____
sn
t
ZH
emiTZ-hgiHtuptuO
)2,1(
____
51
____
52sn
t
HD
emiTdloHataD
)4(
0
____
0
____
sn
t
ZW
Z-hgiHnituptuOotelbanEetirW
)2,1(
____
51
____
52sn
t
WO
etirW-fo-dnEmorfevitcAtuptuO
)4,2,1(
0
____
0
____
sn
t
DRWS
MES emiTdaeRotetirWgalF
5
____
5
____
sn
t
SPS
MES wodniWnoitnetnoCgalF
5
____
5
____
sn
b21lbt1492
6.42
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
11
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing
(1,3,5,8)
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (t
EW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle.
3. t
WR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE, or R/W.
7. Timing depends on which enable signal is de-asserted first, CE, or R/W.
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of t
WP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the
bus for the required t
DW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
9. To access RAM, CE = V
IL and SEM = VIH. To access Semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
Timing Waveform of Write Cycle No. 2, CE Controlled Timing
(1,3,5,8)
2941 drw 09
t
WC
t
AS
t
WR
t
DW
t
DH
ADDRESS
DATA
IN
CE
or
SEM
R/W
t
AW
t
EW
(3)
(2) (6)
(9)
R/W
t
WC
t
HZ
t
AW
t
WR
t
AS
t
WP
DATA
OUT
(2)
t
WZ
t
DW
t
DH
t
OW
OE
ADDRESS
DATA
IN
CE
(6)
(4) (4)
(3)
2941 drw 08
(7)
(7)
or
SEM
(9)
6.42
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
12
Timing Waveform of Semaphore Read after Write Timing, Either Side
(1)
NOTE:
1. CE = V
IH for the duration of the above timing (both write and read cycle).
2. “DATA
OUT VALID” represents all I/O's (I/O0-I/O7) equal to the semaphore value.
Timing Waveform of Semaphore Write Contention
(1,3,4)
SEM
"A"
2941 drw 11
t
SPS
MATCH
R/W
"A"
MATCH
A
0"A"
-A
2"A"
SIDE "A"
(2)
SEM
"B"
R/W
"B"
A
0"B"
-A
2"B"
SIDE
"B"
(2)
NOTES:
1. D
OR = DOL = VIL, CER = CEL = VIH, Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.
2. “A” may be either left or right port. “B” is the opposite port from “A”.
3. This parameter is measured from R/W
“A” or SEM“A” going HIGH to R/W“B” or SEM“B” going HIGH.
4. If t
SPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
SEM
2941 drw 10
t
AW
t
EW
t
SOP
DATA
0
VALID ADDRESS
t
SAA
R/W
t
WR
t
OH
t
t
ACE
VALID ADDRESS
DATA
IN
VALID
DATA
OUT
t
DW
t
WP
t
DH
t
AS
t
SWRD
t
AOE
t
SOP
Read Cycle
Write Cycle
A
0
-A
2
OE
VALID
(2)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

70V05L15JG

Mfr. #:
Buy 70V05L15JG
Manufacturer:
IDT
Description:
SRAM 8K x 8 3.3v Dual- Port Ram
Lifecycle:
New from this manufacturer.
Delivery:
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