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70V05L25PF8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
6.42
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
16
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
(1)
NOTES:
1. 'X' in part number indicates power rating (S or L).
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6.42
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
17
2941 drw 17
ADDR
"B"
INTERRUPT CLEAR ADDRESS
CE
"B"
OE
"B"
t
AS
t
RC
(3)
t
INR
(3)
INT
"B"
(2)
Waveform of Interrupt Timing
(1)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt Truth Table III.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
2941 drw 16
ADDR
"A"
INTERRUPT SET ADDRESS
CE
"A"
R/W
"A"
t
AS
t
WC
t
WR
(3)
(4)
t
INS
(3)
INT
"B"
(2)
6.42
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
18
Truth Table IV — Address BUSY
Arbitration
NOTES:
1. Pins BUSY
L and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the IDT70V05 are push
pull, not open drain outputs. On slaves the BUSY
X input internally inhibits writes.
2. V
IL if the inputs to the opposite port were stable prior to the address and enable inputs of this port. VIH if the inputs to the opposite port became stable after the address and
enable inputs of this port. If t
APS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be low simultaneously.
3. Writes to the left port are internally ignored when BUSY
L outputs are driving low regardless of actual logic level on the pin. Writes to the right port are internally ignored when
BUSY
R outputs are driving low regardless of actual logic level on the pin.
Truth Table V — Example of Semaphore Procurement Sequence
(1,2,3)
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V05.
2. There are eight semaphore flags written to via I/O
0 and read from all I/O's (I/O0-I/O7). These eight semaphores are addressed by A0-A2.
3. CE = V
IH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
Truth Table III — Interrupt Flag
(1)
NOTES:
1. Assumes BUSY
L = BUSYR = VIH.
2. If BUSY
L = VIL, then no change.
3. If BUSY
R = VIL, then no change.
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P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

70V05L25PF8

Mfr. #:
Buy 70V05L25PF8
Manufacturer:
IDT
Description:
SRAM 8K x 8 3.3v Dual- Port Ram
Lifecycle:
New from this manufacturer.
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