LTC1623CMS8#PBF

7
LTC1623
OPERATIO
U
SMBus Operation
SMBus is a serial bus interface that uses only two bus
lines, DATA and CLK, to control low power peripheral
devices in portable equipment. It consists of masters, also
known as hosts, and slave devices. The master of the
SMBus is always the one to initiate communications to its
slave devices by varying the status of the DATA and CLK
lines. The SMBus specification establishes a set of proto-
cols that devices on the bus must follow during commu-
nications.
The protocol that the LTC1623 uses is the Send Byte
Protocol. In this protocol, the master first sends out a Start
signal by switching the DATA line from high to low while
CLK is high. (Because there may be more than one master
on the same bus, an arbitration process takes place if two
masters attempt to take control of the DATA line simulta-
neously; the first master that outputs a one while the other
master is zero loses the arbitration and becomes a slave
itself.) Upon detecting this Start signal, all slave devices on
the bus wake up and get ready to shift in the next byte of
data.
The master then sends out the first byte. The first seven
bits of this byte consist of the address of the device that the
master wishes to communicate with. The last bit indicates
whether the command will be a read (logic one) or write
(logic zero). Because the LTC1623 is a slave device that
can only be written to by a master, it will ignore the ensuing
commands of the master if it wants to read from the
LTC1623, even if the address sent by the master matches
that of the LTC1623. After reception of the first byte, the
slave device (LTC1623) with the matching address then
acknowledges the master by pulling the data line low
before the rising edge of the ninth clock cycle.
By now, all other nonmatching slave devices will have
gone back to their original standby states to wait for the
next start signal. Meanwhile, upon receiving the acknowl-
edge from the matching slave, the master then sends out
the command byte. In the case of the LTC1623, the two
LSBs of this second byte from the master are the signals
controlling the status of the external switches; a digital
“one” turns on the charge pump to drive up the output gate
voltage while a digital “zero” shuts down the charge pump
and discharges the output gate voltage to zero.
After receiving the command byte, the slave device
(LTC1623) needs to again acknowledge the master by
pulling the DATA line low on the following clock cycle. The
master then ends this Send Byte Protocol by sending the
Stop signal, which is a transition from low to high on the
DATA line while the CLK line is high. Valid data is shifted
into the output latch on the last acknowledge signal; the
external switch will not be enabled, however, until the Stop
signal is detected. This double-buffering feature allows
the user to daisy-chain several differently addressed SMBus
devices such that their output executions are synchronous
to the Stop signal even though valid data were loaded into
their output latches at different times. Figure 1 shows an
example of this special protocol. If somehow either the
Start or the Stop signal is detected in the middle of a byte,
the slave device (LTC1623) will regard this as an error and
reject all previous data. Other than the Stop and Start
conditions, DATA must be stable during CLK high; DATA
can change state only during CLK low.
CLK
START
DATA
1
11
0 000
0
00000
01
(GB ON)
(GA ON)
1623 TD02
COMMAND BYTEADDRESS BYTE
1 ACK STOP
ACK
(PROGRAMMABLE)
(WRITE)
Example of Send Byte Protocol to Slave Address 1011000 Turning GA and GB On
COMMANDADD1 A A STOPADD2 ASTARTSTART COMMAND A COMMAND AADD3 ASTART
1623 F01
Figure 1. Daisy-Chaining Multiple SMBus Devices
8
LTC1623
Address
The LTC1623 has an address of 1011XXX; the four MSBs
are hard-wired, but the 3 LSBs are programmed by the
user with the help of two three-state address pins. Refer to
Table 1 for the pin configurations and their corresponding
addresses.
To conserve standby current, it is preferable to tie the
address pins to either V
CC
or GND. If more than four
addresses are needed, then either one of the address pins
can be tied to the third state of V
CC
/2 by using two equal
value resistors (1M) shown in Figure 2. Do not connect
both address pins to the V
CC
/2 state simultaneously
because this is not a valid address.
Charge Pump
To fully enhance the external N-channel switches, an
internal charge pump is used to boost the output gate drive
to a minimum of 2.7V and a maximum of 6V above V
CC
,
depending on V
CC
itself. The reason for the maximum
output voltage limit is to avoid switch gate source break-
down due to excessive gate overdrive. A feedback network
is used to limit the charge pump output to 6V above V
CC
.
Because the output will only need to drive the gate of the
external switch by charging and discharging the parasitic
gate capacitances, the internal charge pump, clocked by
an approximately 300KHz oscillator, is appropriately sized
to source less than 100µA.
Power-On Reset and Undervoltage Lockout
The LTC1623 starts up with both gate drives low. An
internal power-on reset (POR) signal inhibits operation
until about 300µs after V
CC
crosses the undervoltage
lockout threshold (typically 2V). The circuit includes some
hysteresis and delay to avoid nuisance resets. Once opera-
tion begins, V
CC
must drop below the threshold for at least
100µs to trigger another POR sequence.
During standby, when both gate drive outputs are dis-
abled, quiescent current is kept to a minimum (13µA
typical) because only the UVLO block is active.
Input Threshold
Anticipating the trend toward lower supply voltages, the
SMBus is specified with a V
IH
of 1.4V and a V
IL
of 0.6V.
While some SMBus parts may violate this stringent SMBus
specification by allowing a higher V
IH
value for a corre-
spondingly higher input supply voltage, the LTC1623
meets and maintains the constant SMBus input threshold
specification across the entire supply voltage range of
2.7V to 5.5V.
Figure 2. LTC1623 Programmed with Address 1011001
1
2
3
4
8
7
6
5
V
CC
GA
GB
AD1
DATA
CLK
AD0
GND
DATA
CLOCK
LTC1623
LOAD1
1M
1M
LOAD2
1623 F02
Table 1. Address Pin Truth Table
AD0 AD1 ADDRESS
GND GND 1011000
GND V
CC
/2 1011001
GND V
CC
1011010
V
CC
/2 GND 1011011
V
CC
/2 V
CC
/2 UNUSED
V
CC
/2 V
CC
1011100
V
CC
GND 1011101
V
CC
V
CC
/2 1011110
V
CC
V
CC
1011111
OPERATIO
U
9
LTC1623
APPLICATIONS INFORMATION
WUU
U
To avoid turning on the external power MOSFETs too
quickly, an internal 10k resistor has been placed in series
with each of the output gate drive pins (see Functional
Block Diagram). Therefore, it only needs an external 0.1µF
capacitor to create enough RC delay (10k • 0.1µF = 1ms)
to slow down the ramp rate of the output gate drive. In
other words, it will take a minimum of 1ms to charge up
the external MOSFET. An additional external 1k resistor
between the 0.1µF capacitor and the gate of the MOSFET
(Figure 3) is required to eliminate possible MOSFET self
oscillations.
GA
GB
LTC1623
GND
V
CC
3.5V TO 5.5V
V
CC
0.1µF
1k
13
8
680
56
3.3k
V
OUT
3.3V
10k
10µF
CLK
DATA
(PROGRAMMABLE)
(FROM SMBus)
AD0
AD1
510pF
LOAD
Si3442DV
Si3442DV
LT1431
1623 F04
470µF
6V
+
Figure 4. 3.3V/3A Extremely Low Voltage Drop
Regulator and Load Switch
Figure 3. Dual Load Switch with Q2 On upon Power-Up
V
CC
2.7V TO 5.5V
10µF
(PROGRAMMABLE)
FAN
DISPLAY
1623 F03
(FROM
SMBus)
LTC1623
GND
V
CC
AD0
AD1
CLK
DATA
GA
GB
0.1µF
Q1
Si3442DV
Q2
Si6433DQ
0.1µF
1k
1k
Figure 6. Switching Regulator with Low-Battery
Detect Using 22µA Standby Current
V
CC
2.7V TO 4.5V
0.1µF
100µF
1k
3
8
4
2
499k
5
7
LBO
22µH*
*SUMIDA CD54-220
604k
10µF
(PROGRAMMABLE)
(FROM
SMBus)
1N5817
LOAD
SHDN
Si3442DV
Si3442DV
LT1304-5
1623 F05
+
2200µF
5V
200mA
100k
+
GA
GB
LTC1623
GND
V
CC
CLK
DATA
AD0
AD1
GA
GB
LTC1623
GND
V
CC
3.5V TO 5.5V
V
CC
13
8
680
56
3.3k
V
OUT
3.3V
SWITCHED
V
OUT
3.3V
10k
10µF
CLK
DATA
(PROGRAMMABLE)
(FROM SMBus)
AD0
AD1
510pF
0.1µF
Si3442DV
LT1431
1623 TA03
1k
470µF
6V
Si3442DV
+
Figure 5. SMBus Controlled Low Dropout Regulator
For active-low applications in which the load needs to be
on upon power-up, an external P-channel switch can be
used (Figure 3). This load can be switched off later after the
proper protocol has been sent.
Used with the LT
®
1431, the LTC1623 makes a 3.3V/3A
extremely low voltage drop regulator (Figures 4 and 5). In
this application, the other output channel can be used to
drive a separate load, or it can also be used to control the
output of the LDO so that the user has total control over the
switching in and switching out of the LDO (Figure 5). Also,
with the help of the LT1304-5, the LTC1623 can be used
to make a boost switching regulator with a low standby
current of 22µA (Figure 6).

LTC1623CMS8#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Gate Drivers SMBus 2x Hi-SideSwitch Cntr
Lifecycle:
New from this manufacturer.
Delivery:
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