DS_
T48SR05005_09282012
5
ELECTRICAL CHARACTERISTICS CURVES
Figure 8: Output voltage response to step-change in load
current (75%-50% of Io, max; di/dt =1A/µs). Load cap: 400µF,
ceramic capacitor. Top Trace: Vout (100mV/div,200us/div);
Bottom Trace: output current(1.5A/div, 200us/div)
Figure 9: Output voltage response to step-change in load
current (50%-75% of Io, max; di/dt =1A/µs). Load cap: 400µF
ceramic capacitor. Top Trace: Vout (100mV/div,200us/div);
Bottom Trace: output current(1.5A/div, 200us/div)
Figure 10: Test set-up diagram showing measurement points
for Input Terminal Ripple Current and Input Reflected Ripple
Current.
Top picture: standard test setup.
Bottom picture: Add one 1uH inductor in front of module input.
Note: Measured input reflected-ripple current with a simulated
source Inductance (L
TEST
) of 12 µH. Capacitor Cs offset
possible battery impedance. Measure current as shown above.
Figure 11: Top trace: Input Terminal Ripple Current, i
c
, at full
rated output current and nominal input voltage with 12µH
source impedance and 100µF electrolytic capacitor (2A/div
，
2us/div), Setup is shown in Figure 10 top picture.
Bottom trace: Input Terminal Ripple Current, i
c
, at
full rated output current and nominal input voltage with 12µH
source impedance and 100µF electrolytic capacitor (2A/div
，
2us/div), Setup is shown in Figure 10 bottom picture, there is
one 1uH inductor in front of module input side.
