P1P8160AG-10CR Datasheet P1P8160AG-10CR | P1-P3

October, 2010 − Rev. 2

1 Publication Order Number:

P1P8160A/D

P1P8160A

Low Jitter Clock Generator

and Peak EMI Reduction IC

Product Description

P1P8160A is a versatile low jitter clock generator and spread

spectrum frequency modulator designed to reduce electromagnetic

interference (EMI) at the clock source, allowing system wide

reduction of EMI of down stream clock and data dependent signals.

The device allows significant system cost savings by reducing the

number of circuit board layers ferrite beads, shielding and other

passive components that are traditionally required to pass EMI

regulations.

P1P8160A modulates the output of a PLL in order to “spread” the

bandwidth of a synthesized clock, and more importantly, decreases the

peak amplitudes of its harmonics. This results in significantly lower

system EMI compared to the typical narrow band signal produced by

oscillators and most frequency generators. Lowering EMI by

increasing a signal’s bandwidth is called ‘spread spectrum clock

generation’.

P1P8160A accepts an input from either a 27 MHz fundamental

Crystal or from an external reference clock and generates a 100 MHz

Spread Spectrum clock. The device also features a 27MHz reference

clock output. Two Tri−level logic pins, SS1% and SS2% enables

selecting one of the eight different frequency deviations along with

SSOFF. Refer to Frequency Deviation Selection table. P1P8160A

operates over a supply voltage range of 3.3 V ± 10%. P1P8160A is

available in a 10 Pin WDFN (3 mm x 3 mm) package, over

temperature range −10°C to +85°C.

Features

• LVCMOS Peak EMI Reduction

• Input clock Frequency:

27 MHz: External Crystal or Reference Clock

• Output clock Frequencies:

100 MHz Spread Spectrum Clock

27 MHz Refout

• Two Tri−level Logic Pins for Selecting Eight Different Frequency

Deviations Along with SSOFF

• Modulation Rate at 100 MHz: 32 kHz

• Low Cycle−Cycle Jitter, LT Jitter

• Supply voltage: 3.3 V ± 10%

• Temperature Range: −10°C to +85°C

• 10 Pin WDFN, 3 mm x 3 mm Package

• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

Application

• P1P8160A is targeted for use in a broad range of notebook, desktop

and embedded digital applications.

WDFN10

CASE 511BK

MARKING

DIAGRAM

http://onsemi.com

CLKIN/XIN

VSS

SS2%

VDD1

VDD2

XOUT

SS1%

RefOUT

PIN CONFIGURATION

See detailed ordering and shipping information in the package

dimensions section on page 5 of this data sheet.

ORDERING INFORMATION

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

G = Pb−Free Package

8160A

ALYWG

VSS

ModOUT

P1P8160A

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VDD2

VSS

CLKIN/XIN

RefOUT

PLL

SS1%

XOUT

SS2%

ModOUT

Crystal

Oscillator

Figure 1. Block Diagram

VDD1

Table 1. PIN DESCRIPTION

Pin# Pin Name Type Description

1 CLKIN / XIN I Crystal connection or External Reference Clock Input.

2 VSS P Ground to entire chip

3 SS2% I Frequency Deviation Selection. Tri−level logic pin. Has an internal pull down resistor.

Refer to Frequency Deviation Selection table

4 VDD1 Supply Voltage for 100 MHz ModOUT

5 ModOUT O Buffered 100MHz spread spectrum clock output

6 VSS P Ground to entire chip

7 SS1% I Frequency Deviation Selection. Tri−level logic pin. Has an internal pull down resistor.

Refer to Frequency Deviation Selection table

8 VDD2 P Supply Voltage for 27 MHz RefOUT

9 RefOUT O Buffered reference clock output

10 XOUT O Crystal connection. If using an external reference, this pin must be left unconnected.

3 Level Digital Logic

SS1% and SS2% digital inputs are designed to sense 3

different logic levels designated as High “1”, Low “0” and

Middle “M”. With this 3−Level digital inputs, 9 different

logic states can be detected.

Use 5k/5k resistor divider at SS1% and SS2% pins from

to V

to obtain V

/2, Middle “M” logic level as

shown:

Logic Control Pins

1 SS1%, SS2% to V

VSS

VDD

VSS

VDD

M SS1%, SS2%

SS1%, SS2% to V

(UNCONNECTED)

P1P8160A

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Table 2. FREQUENCY DEVIATION SELECTION TABLE

SS2% (Pin#3) SS1% (Pin#7) Deviation at 100 MHz (%) (Pin#5) ModRate (kHz)

L L SSOFF

L M −0.5

L H −2.5

M L −0.25

M M −0.75

M H −1

H L −1.5

H M −2

H H −3

Table 3. OPERATING CONDITIONS

Symbol Parameter Min Max Unit

Voltage on any pin with respect to VSS 2.97 3.63 V

Operating Temperature −10 +85 °C

Load Capacitance 15 pF

Input Capacitance 7 pF

Table 4. ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Rating Unit

, V

Voltage on any pin with respect to Ground −0.5 to +4.6 V

STG

Storage Temperature −65 to +125 °C

Max. Soldering Temperature (10 sec) 260 °C

Junction Temperature 150 °C

Static Discharge Voltage (As per JEDEC STD 22− A114−B) 2 kV

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may

affect device reliability.

Table 5. DC ELECTRICAL CHARACTERISTICS

= 3.3 V ± 10%, Ambient Temperature Range: −10°C to +85°C unless otherwise specified)

Symbol

Parameter Min Typ Max Unit

Supply Voltage 2.97 3.3 3.63 V

Input Low Voltage (CLKIN/XIN, SS1%, SS2% Inputs) 0 0.2 V

Input Middle Voltage (SS1%, SS2% Inputs) 0.4 x V

0.6 x V

Input High Voltage (CLKIN/XIN, SS1%, SS2% Inputs) 0.9 x V

Output Low Voltage (ModOUT, RefOUT) I

= 15 mA 0.4 V

Output High Voltage (ModOUT, RefOUT) I

= −15 mA 2.4 V

Dynamic Supply Current (C

= 15 pF, V

= 3.63 V, T = +85°C) 22 mA

IN1

Input Capacitance (XIN and XOUT) 6.0 pF

IN2

Input Capacitance (SS1%, SS2% Inputs) 7.0 pF

Pull Down Resistor (SS1%, SS2% Inputs) 100 200 250

NOTE: The voltage on any input or I/O pin cannot exceed the power pin during power up.

P1-P3 P4-P6

P1P8160AG-10CR

Mfr. #:

Buy P1P8160AG-10CR

Manufacturer:

ON Semiconductor

Description:

Clock Synthesizer / Jitter Cleaner 3.3V LOW JITTER CG

Lifecycle:

New from this manufacturer.

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