© 2007 Microchip Technology Inc. DS21948D-page 7
MCP3905/06
Note: Unless otherwise specified, DV
DD
, AV
DD
= 5V; A
GND
, D
GND
= 0V; V
REF
= Internal, HPF = 1 (AC mode),
MCLK = 3.58 MHz.
FIGURE 2-11: Measurement Error vs.
Input Frequency.
FIGURE 2-12: Channel 0 Offset Error
(DC Mode, HPF off), G = 1.
FIGURE 2-13: Channel 0 Offset Error
(DC Mode, HPF off), G = 8.
FIGURE 2-14: Channel 0 Offset Error
(DC Mode, HPF Off), G = 16.
FIGURE 2-15: Measurement Error vs. V
DD
(G = 16).
FIGURE 2-16: Measurement Error vs. V
DD
,
G = 16, External V
REF
.
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
45 50 55 60 65 70 75
Frequency (Hz)
% Error
PF = 1.0
PF = 0.5
0
500
1000
1500
2000
2500
3000
-1.75
-1.70
-1.65
-1.61
-1.56
-1.52
-1.47
-1.43
-1.38
Channel 0 Offset (mV)
Occurance
16384 Samples
Mean = -1.57 mV
Std. Dev = 52.5 µV
0
200
400
600
800
1000
1200
-1.71
-1.69
-1.68
-1.67
-1.66
-1.65
-1.64
-1.63
-1.62
-1.60
-1.59
Channel 0 Offset (mV)
Occurance
16384 Samples
Mean = -1.64 mV
Std. Dev = 17.4 µV
0
500
1000
1500
2000
2500
3000
3500
4000
-1.38E-03
-1.37E-03
-1.36E-03
-1.35E-03
-1.34E-03
-1.33E-03
-1.32E-03
-1.31E-03
-1.30E-03
-1.29E-03
-1.28E-03
-1.27E-03
-1.26E-03
-1.25E-03
-1.24E-03
-1.23E-03
-1.22E-03
Bin (mV)
Occurance
16384 Samples
Mean = - 1.28 mV
Std. dev = - 18.1 µV
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.0001 0.0010 0.0100 0.1000 1.0000
CH0 Vp-p Amplitude (V)
Measurement Error
V
DD
=4.75V
V
DD
=5.0V
V
DD
=4.5V
V
DD
=5.25V
V
DD
=5.5V
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
0.25
0.3
0.0001 0.0010 0.0100 0.1000 1.0000
CH0 Vp-p Amplitude (V)
Measurement Error
V
DD
=4.5V
V
DD
=4.75V
V
DD
=5.0V
V
DD
=5.25V
V
DD
=5.5V
MCP3905/06
DS21948D-page 8 © 2007 Microchip Technology Inc.
Note: Unless otherwise specified, DV
DD
, AV
DD
= 5V; A
GND
, D
GND
= 0V; V
REF
= Internal, HPF = 1 (AC mode),
MCLK = 3.58 MHz.
FIGURE 2-17: Measurement Error
w/ External V
REF
, (G = 1).
FIGURE 2-18: Measurement Error
w/ External V
REF
, (G = 8).
FIGURE 2-19: Measurement Error
w/ External V
REF
(G = 16).
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.0001 0.0010 0.0100 0.1000 1.0000
CH0 Vp-p Amplitude (V)
Measurement Error
+85°C
+25°C
- 40°C
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.0000 0.0001 0.0010 0.0100 0.1000
CH1 Vp-p Amplitude (V)
Measurement Error
+85°C
+25°C
-40°C
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.0000 0.0001 0.0010 0.0100 0.1000
CH1 Vp-p Amplitude (V)
Measurement Error
+85°C
+25°C
- 40°C
© 2007 Microchip Technology Inc. DS21948D-page 9
MCP3905/06
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
3.1 Digital V
DD
(DV
DD
)
DV
DD
is the power supply pin for the digital circuitry
within the MCP3905/06.
DV
DD
requires appropriate bypass capacitors and
should be maintained to 5V ±10% for specified
operation. Please refer to Section 5.0 “Applications
Information.
3.2 High-Pass Filter Input Logic Pin
(HPF)
HPF controls the state of the high-pass filter in both
input channels. A logic ‘1’ enables both filters,
removing any DC offset coming from the system or the
device. A logic ‘0’ disables both filters, allowing DC
voltages to be measured.
3.3 Analog V
DD
(AV
DD
)
AV
DD
is the power supply pin for the analog circuitry
within the MCP3905/06.
AV
DD
requires appropriate bypass capacitors and
should be maintained to 5V ±10% for specified
operation. Please refer to Section 5.0 “Applications
Information”.
3.4 Current Channel (CH0-, CH0+)
CH0- and CH0+ are the fully differential analog voltage
input channels for the current measurement, containing
a PGA for small-signal input, such as shunt current-
sensing. The linear and specified region of this channel
is dependant on the PGA gain. This corresponds to a
maximum differential voltage of ±470 mV/GAIN and
maximum absolute voltage, with respect to A
GND
, of
±1V. Up to ±6V can be applied to these pins without the
risk of permanent damage.
Refer to Section 1.0 “Electrical Characteristics”.
Pin No. Symbol Function
1DV
DD
Digital Power Supply Pin
2 HPF High-Pass Filters Control Logic Pin
3AV
DD
Analog Power Supply Pin
4 NC No Connect
5 CH0+ Non-Inverting Analog Input Pin for Channel 0 (Current Channel)
6 CH0- Inverting Analog Input Pin for Channel 0 (Current Channel)
7 CH1- Inverting Analog Input Pin for Channel 1 (Voltage Channel)
8 CH1+ Non-Inverting Analog Input Pin for Channel 1 (Voltage Channel)
9MCLR
Master Clear Logic Input Pin
10 REFIN/OUT Voltage Reference Input/Output Pin
11 A
GND
Analog Ground Pin, Return Path for internal analog circuitry
12 F2 Frequency Control for HF
OUT
Logic Input Pin
13 F1 Frequency Control for F
OUT0/1
Logic Input Pin
14 F0 Frequency Control for F
OUT0/1
Logic Input Pin
15 G1 Gain Control Logic Input Pin
16 G0 Gain Control Logic Input Pin
17 OSC1 Oscillator Crystal Connection Pin or Clock Input Pin
18 OSC2 Oscillator Crystal Connection Pin or Clock Output Pin
19 NC No Connect
20 NEG Negative Power Logic Output Pin
21 D
GND
Digital Ground Pin, Return Path for Internal Digital Circuitry
22 HF
OUT
High-Frequency Logic Output Pin (Intended for Calibration)
23 F
OUT1
Differential Mechanical Counter Logic Output Pin
24 F
OUT0
Differential Mechanical Counter Logic Output Pin

MCP3906-I/SS

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