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85314BMI-01LF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
Low Skew, 1-to-5
Differential-to-2.5V/3.3V LVPECL Fanout Buffer
85314I-01
DATASHEET
85314I-01 REVISION G DECEMBER 19, 2014 1 ©2014 Integrated Device Technology, Inc.
GENERAL DESCRIPTION
The 85314I-01 is a low skew, high performance 1-to-
5 Differential-to-2.5V/3.3V LVPECL Fanout Buffer.The
85314I-01 has two selectable clock inputs. The CLK0,
nCLK0 pair can accept most standarddifferential input
levels. The single-ended CLK1 can accept LVCMOS or
LVTTL input levels. The clock enable is internally
synchronized to eliminate runt clock pulses on the outputs during
asynchronous assertion/deassertion of the clockenable pin.
Guaranteed output and part-to-part skew character-
istics make the 85314I-01 ideal for those applications
demanding well defi ned performance and repeatability.
FEATURES
• 5 differential 2.5V/3.3V LVPECL outputs
• Selectable differential CLK0, nCLK0 or LVCMOS inputs
• CLK0, nCLK0 pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• CLK1 can accept the following input levels:
LVCMOS or LVTTL
• Maximum output frequency: 700MHz
• Translates any single-ended input signal to 3.3V
LVPECL levels with resistor bias on nCLK input
• Output skew: 30ps (maximum), TSSOP package
50ps (maximum), SOIC package
• Part-to-part skew: 350ps (maximum)
• Propagation delay: 1.8ns (maximum)
• RMS phase jitter @ 155.52MHz (12kHz - 20MHz):
0.05ps (typical)
• LVPECL mode operating voltage supply range:
V
CC
= 2.375V to 3.8V, V
EE
= 0V
• -40°C to 85°C ambient operating temperature
• Available in lead-free RoHS-compliant package
BLOCK DIAGRAM PIN ASSIGNMENT
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
nCLK_EN
V
CC
nc
CLK1
CLK0
nCLK0
nc
CLK_SEL
V
EE
85314I-01
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm Package Body
G Package
Top View
85314I-01
20-Lead SOIC
7.5mm x 12.8mm x 2.3mm Package Body
M Package
Top View
Low Skew, 1-to-5
Differential-to-2.5V/3.3V LVPE
CL Fanout Buffer
85314I-01 DATA SHEET
2 REVISION G 12/19/14
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
R
PULLUP
Input Pullup Resistor 51
kΩ
R
PULLDOWN
Input Pulldown Resistor 51
kΩ
Number Name Type Description
1, 2 Q0, nQ0 Output Differential output pair. LVPECL interface levels.
3, 4 Q1, nQ1 Output Differential output pair. LVPECL interface levels.
5, 6 Q2, nQ2 Output Differential output pair. LVPECL interface levels.
7, 8 Q3, nQ3 Output Differential output pair. LVPECL interface levels.
9, 10 Q4, nQ4 Output Differential output pair. LVPECL interface levels.
11 V
EE
Power Negative supply pin.
12 CLK_SEL Input Pulldown
Clock select input. When HIGH, selects CLK1 input.
When LOW, selects CLK0, nCLK0 inputs.
LVTTL / LVCMOS interface levels.
13, 17 nc Unused No connect.
14 nCLK0 Input Pullup Inverting differential clock input.
15 CLK0 Input Pulldown Non-inverting differential clock input.
16 CLK1 Input Pulldown Clock input. LVTTL / LVCMOS interface levels.
18, 20 V
CC
Power Positive supply pins.
19 nCLK_EN Input Pulldown
Synchronizing clock enable. When LOW, clock outputs follow clock input.
When HIGH, Q outputs are forced low, nQ outputs are forced high. LVT-
TL / LVCMOS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
REVISION G 12/19/14
85314I-01 DATA SHEET
3 Low Skew, 1-to-5
Differential-to-2.5V/3.3V LVPECL Fanout Buffer
TABLE 3A. CONTROL INPUT FUNCTION TABLE
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs Outputs
nCLK_EN CLK_SEL Selected Source Q0:Q4 nQ0:nQ4
0 0 CLK0, nCLK0 Enabled Enabled
0 1 CLK1 Enabled Enabled
1 0 CLK0, nCLK0 Disabled; LOW Disabled; HIGH
1 1 CLK1 Disabled; LOW Disabled; HIGH
After nCLK_EN switches, the clock outputs are disabled or enabled following a falling input clock edge
as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK0, nCLK0 and CLK1 inputs
as described in Table 3B.
Inputs Outputs
Input to Output Mode Polarity
CLK0 or CLK1 nCLK0 Q0:Q4 nQ0:nQ4
0 1 LOW HIGH Differential to Differential Non Inverting
1 0 HIGH LOW Differential to Differential Non Inverting
FIGURE 1. nCLK_EN TIMING DIAGRAM
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

85314BMI-01LF

Mfr. #:
Buy 85314BMI-01LF
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 5 LVPECL OUT BUFFER
Lifecycle:
New from this manufacturer.
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