IRLML2803TRPBF

P1-P3 P4-P6 P7-P9

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IRLML2803PbF

Fig 7. Typical Source-Drain Diode

Forward Voltage

Fig 5. Typical Capacitance Vs.

Drain-to-Source Voltage

Fig 8. Maximum Safe Operating Area

Fig 6. Typical Gate Charge Vs.

Gate-to-Source Voltage

0

20

40

60

80

100

120

140

160

1 10 100

C, Capacitance (pF)

DS

V , Drain-to-Source Voltage (V)

A

V = 0V, f = 1MHz

C = C + C , C SHORTED

C = C

C = C + C

GS

iss gs gd ds

rss gd

oss ds gd

C

iss

C

oss

C

rss

0

4

8

12

16

20

0.0 1.0 2.0 3.0 4.0 5.0

Q , Total Gate Charge (nC)

G

V , Gate-to-Source Voltage (V)

GS

A

FOR TEST CIRCUIT

SEE FIGURE 9

I = 0.91A

V = 24V

V = 15V

D

DS

DS

0.1

1

10

0.4 0.6 0.8 1.0 1.2 1.4

T = 25°C

T = 150°C

J

J

V = 0V

GS

V , Source-to-Drain Voltage (V)

I , Reverse Drain Current (A)

SD

SD

A

0.1

1

10

100

1 10 100

V , Drain-to-Source Voltage (V)

DS

I , Drain Current (A)

OPERATION IN THIS AREA LIMITED

BY R

D

DS(on)

T = 25°C

T = 150°C

Single Pulse

1ms

10ms

A

A

J

100μs

10μs

5 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback April 24, 2014

IRLML2803PbF

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient

V

DS

90%

10%

V

GS

t

d(on)

t

r

t

d(off)

t

f

Fig 10a. Switching Time Test Circuit

Fig 10b. Switching Time Waveforms

V

DS

10V

Pulse Width ≤ 1 µs

Duty Factor ≤ 0.1 %

R

D

V

GS

V

DD

R

G

D.U.T.

+

-

Fig 9a. Basic Gate Charge Waveform

D.U.T.

V

DS

I

D

I

G

3mA

V

GS

.3μF

50KΩ

.2μF

12V

Current Regulator

Same Type as D.U.T.

Current Sampling Resistors

+

-

Q

G

Q

GS

Q

GD

V

G

Charge

10V

Fig 9b. Gate Charge Test Circuit

0.1

1

10

100

1000

0.00001 0.0001 0.001 0.01 0.1 1 10 100

Notes:

1. Duty factor D = t / t

2. Peak T = P x Z + T

1 2

J DM thJA A

P

t

t

DM

1

2

t , Rectangular Pulse Duration (sec)

Thermal Response (Z )

1

thJA

0.01

0.02

0.05

0.10

0.20

D = 0.50

SINGLE PULSE

(THERMAL RESPONSE)

6 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback April 24, 2014

IRLML2803PbF

Fig 13. Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET

®

Power MOSFETs

Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

• Low Leakage Inductance

Current Transformer

P.W.

Period

di/dt

Diode Recovery

dv/dt

Ripple ≤ 5%

Body Diode Forward Drop

Re-Applied

Voltage

Reverse

Recovery

Current

Body Diode Forward

Current

V

GS

=10V

V

DD

I

SD

Driver Gate Drive

D.U.T. I

SD

Waveform

D.U.T. V

DS

Waveform

Inductor Curent

D =

P. W .

Period

* V

GS

= 5V for Logic Level Devices

*

+

-

+

+

+

-

-

-







R

G

V

DD

• dv/dt controlled by R

G

• Driver same type as D.U.T.

• I

SD

controlled by Duty Factor "D"

• D.U.T. - Device Under Test

D.U.T



Fig 12c. Maximum Avalanche Energy

vs. Drain Current

Fig 12b. Unclamped Inductive Waveforms

Fig 12a. Unclamped Inductive Test Circuit

t

p

V

(BR)DSS

I

AS

R

G

I

AS

0.01

Ω

t

p

D.U.T

L

V

DS

+

-

V

DD

DRIVER

A

15V

20V

V

GS

25 50 75 100 125 150

Starting T

J

, Junction Temperature (°C)

0

2

4

6

8

10

12

14

16

18

E

A

S

,

S

i

n

g

l

e

P

u

l

s

e

A

v

a

l

a

n

c

h

e

E

n

e

r

g

y

(

m

J

)

I

D

TOP 0.57A

0.75A

BOTTOM

0.90A

P1-P3 P4-P6 P7-P9

IRLML2803TRPBF

Mfr. #:

Buy IRLML2803TRPBF

Manufacturer:

Infineon Technologies

Description:

MOSFET MOSFT 30V 1.2A 250mOhm 3.3nC LogLvl

Lifecycle:

New from this manufacturer.

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IRLML2803TRPBF