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843S1333DGLF

P1-P3P4-P6P7-P9P10-P12P13-P15
7©2015 Integrated Device Technology, Inc Revision A December 2, 2015
843S1333D Data Sheet
Overdriving the XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3A. The XTAL_OUT pin can be left floating. The
maximum amplitude of the input signal should not exceed 2V and the
input edge rate can be as slow as 10ns. This configuration requires
that the output impedance of the driver (Ro) plus the series
resistance (Rs) equals the transmission line impedance. In addition,
matched termination at the crystal input will attenuate the signal in
half. This can be done in one of two ways. First, R1 and R2 in parallel
should equal the transmission line impedance. For most 50
applications, R1 and R2 can be 100. This can also be
accomplished by removing R1 and making R2 50. By overdriving
the crystal oscillator, the device will be functional, but note, the device
performance is guaranteed by using a quartz crystal.
Figure 3A. General Diagram for LVCMOS Driver to XTAL Input Interface
Figure 3B. General Diagram for LVPECL Driver to XTAL Input Interface
8©2015 Integrated Device Technology, Inc Revision A December 2, 2015
843S1333D Data Sheet
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 4A and 4B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
Figure 4A. 3.3V LVPECL Output Termination Figure 4B. 3.3V LVPECL Output Termination
R1
84
R2
84
3.3V
R3
125
R4
125
Z
o
= 50
Z
o
= 50
Input
3.3V
3.3V
+
_
9©2015 Integrated Device Technology, Inc Revision A December 2, 2015
843S1333D Data Sheet
Schematic Example
Figure 5 shows an example of the ICS843S133D application
schematic. In this example, the device is operated at V
CC
= 3.3V. The
18pF parallel resonant 20MHz crystal is used. The C1 and C2 = 28pF
are recommended for frequency accuracy. For different board layout,
the C1 and C2 may be slightly adjusted for optimizing frequency
accuracy. Two examples of LVPECL termination are shown in this
schematic. Additional termination approaches are shown in the
LVPECL Termination Application Note.
Figure 5. 843S1333D Schematic Example
R4
82.5
Set Logic
Input to
'0'
VCCA
C1
28pF
+
-
VCC
C2
28pF
C5
0.01u
Zo = 50 Ohm
OE
Zo = 50 Ohm
VCC=3.3V
R3
133
RU1
1K
VCC
VCC
Set Logic
Input to
'1'
R5
82.5
XTAL_IN
Logic Control Input Examples
C4
10uF
RD2
1K
VCC
VCC
XTA L_ OU T
Optional
Y-Termination
+
-
R6
50
nQ
3.3V
Zo = 50 Ohm
RD1
Not Install
R8
50
R2
133
R7
50
Zo = 50 Ohm
C3
0.01u
To Logic
Input
pins
X1
20MHz
To Logic
Input
pins
R1
10
RU2
Not Install
U1
1
2
3
4
8
7
6
5
VCCA
VEE
XTAL _O UT
XTAL _I N
VCC
Q
nQ
OE
Q
P1-P3P4-P6P7-P9P10-P12P13-P15

843S1333DGLF

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Buy 843S1333DGLF
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner CLOCK SYNTHESIZER
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