OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

NB3N3010BDR2G

P1-P3P4-P6P7-P9
© Semiconductor Components Industries, LLC, 2011
May, 2011 − Rev. 0
1 Publication Order Number:
NB3N3010B/D
NB3N3010B
3.3V, 12.288 MHz Audio
Oversampling Clock
Generator for USB
Applications
Description
The NB3N3010B is a precision, low noise clock multiplier that
generates an output frequency of 12.288 MHz. This is accomplished
by using Frequency−Locked−Loop (FLL) techniques where a 4 kHz
reference input is multiplied by 3072, or an 8 kHz input by 1536. The
frequency multiplier is selected by the S0 pin.
The two LVCMOS output drivers are disabled to a logic Low with
the ENABLEn pin set HIGH. The NB3N3010B operates from a single
+3.3 V supply, and is available in the SOIC−8 pin package, and
optionally in a DFN8 package. The operating temperature range is
from 0°C to +85°C.
The NB3N3010B device provides the optimum combination of low
cost, flexibility, and high performance. This makes it ideal for
applications such as oversampling A−to−D and D−to−A converters
from a low reference frequency, such as a USB start−of−frame (SOF)
pulse.
Features
• Accepts 8 kHz or 4 kHz Reference Input Derived from USB
Start−of−Frame
• Generates 12.288 MHz Frequency−Locked to the Reference
• Fully Integrated Frequency−Lock−Loop with Internal Loop Filter
• Low Skew Dual LVCMOS Outputs
• Very Low Phase Noise Preserves Codec Noise Floor
• Internal Voltage Regulator
• Supply Voltage Required: +3.3 V $5%
• Temperature Range: 0°C to +85°C
• These are Pb−Free Devices
8 4
2
Tolerant
Frequency
Detector
Loop Filter
Frequency
Generator
Output
Buffers
7
Divider
3
REF
S0
CLK_B
VDD GND
1
ENABLEn
+1.8 V
Linear
Regulator
5
CFILT
CLK_A
6
Figure 1. NB3N3010B Simplified Diagram
*For additional marking information, refer to
Application Note AND8002/D.
MARKING
DIAGRAMS*
SOIC−8
D SUFFIX
CASE 751
1
8
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
ORDERING INFORMATION
http://onsemi.com
3010B
ALYW
G
1
8
DFN8
MN SUFFIX
CASE 506AA
XX M G
G
14
(Note: Microdot may be in either location)
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
M = Date Code
G = Pb−Free Package
NB3N3010B
http://onsemi.com
2
Figure 2. Pinout SOIC−8 / DFN8 (Top View)
CLKA
1
2
3
4
8
7
6
5
ENABLEn
S0
REF
GND
VDD
CLKB
CFILT
NB3N3010B
Table 1. PIN DESCRIPTION
Pin Symbol I/O Description
1 ENABLEn LVTTL/
LVCMOS Input
Low active Output Enable; Defaults HIGH when left open; Internal pull−up resistor to
V
DD
.
2 S0 LVTTL/
LVCMOS Input
Frequency Select Input. See input frequency select Table 2 for details. Defaults HIGH
when left open. Internal pull−up resistor to V
DD
.
3 REF Input Reference Clock input
4 GND Power Supply Negative Supply Voltage; Ground 0 V. This pin provides GND return path to the VDD
supply.
5 CFILT Analog Connection for external filter capacitor for internal +1.8 V regulator; see Figure 4.
6 CLKA LVCMOS
Output
Clock output, copy A (12.288 MHz)
7 CLKB LVCMOS
Output
Clock output, copy B (12.288 MHz)
8 VDD Power Supply Positive Supply Voltage, +3.3 V $5%
NB3N3010B
http://onsemi.com
3
Table 2. ATTRIBUTES
Characteristic Value
ESD Protection Human Body Model
Machine Model
> 4 kV
400 V
R
PU
− ENABLEn Input Pull−up Resistor
R
PU
− SO Input Pull−up Resistor
48 kW
48 kW
Moisture Sensitivity (Note 1) Pb−Free Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
Transistor Count 12039
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 3. ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
V
DD
Positive Power Supply GND = 0 V 4.6 V
V
I
Input Voltage (VIN) GND = 0 V −0.3 V to V
DD
+
0.3 V
V
T
A
Operating Temperature Range 0 to +85 °C
T
stg
Storage Temperature Range −40 to +150 °C
q
JA
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
SOIC−8
SOIC−8
190
130
°C/W
°C/W
q
JC
Thermal Resistance (Junction−to−Case) (Note 2) SOIC−8 41 to 44 °C/W
q
JA
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
DFN−8 (2x2)
DFN−8 (2x2)
129
84
°C/W
q
JC
Thermal Resistance (Junction−to−Case) (Note 2) DFN−8 (2x2) 35−40 °C/W
T
sol
Wave Solder Pb−Free 265 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).
Table 4. DC CHARACTERISTICS V
DD
= 3.3 V $5%, GND = 0 V, T
A
= 0°C to +85°C, Note 3.
Symbol Characteristic Min Typ Max Unit
V
DD
Power Supply Voltage 3.13 3.3 3.47 V
I
DDOEL
Power Supply Current (operating, i.e. ENABLEn is LOW) Outputs
Unloaded
21 35 mA
I
DDOEH
Power Supply Current (standby, i.e. ENABLEn is HIGH) 415 600 uA
V
IH
Input HIGH Voltage (REF, ENABLEn, S0) 2.0 V
DD
+ 0.3 V
V
IL
Input LOW Voltage (REF, ENABLEn, S0) GND − 0.3 0.8 V
V
OH
Output HIGH Voltage (CLKA, CLKB) , I
OH
= −12 mA 2.4 V
V
OL
Output LOW Voltage (CLKA, CLKB), I
OL
= 12 mA 0.4 V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. C
FILT
capacitor must be installed; see Figure 4.
P1-P3P4-P6P7-P9

NB3N3010BDR2G

Mfr. #:
Buy NB3N3010BDR2G
Manufacturer:
ON Semiconductor
Description:
Clock Generators & Support Products AUDIO OVERSAMPLING CLOCK
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet