NTD5867NLT4G

NTD5867NL
http://onsemi.com
4
TYPICAL PERFORMANCE CURVES
C
rss
02030
DRAIN−TO−SOURCE VOLTAGE (VOLTS)
C, CAPACITANCE (pF)
Figure 7. Capacitance Variation
10
V
GS
= 0 V
T
J
= 25°C
C
oss
C
iss
V
GS
Figure 8. Gate−To−Source Voltage vs.
Total Charge
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
Q
G
, TOTAL GATE CHARGE (nC)
V
DS
= 48 V
I
D
= 20 A
T
J
= 25°C
Q
gd
Q
gs
Q
T
V
SD
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
I
S
, SOURCE CURRENT (AMPS)
Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
R
G
, GATE RESISTANCE (OHMS)
t, TIME (ns)
V
GS
= 0 V
Figure 10. Diode Forward Voltage vs. Current
t
r
t
d(off)
t
d(on)
t
f
V
DD
= 48 V
I
D
= 20 A
V
GS
= 10 V
T
J
= 25°C
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
I
D
, DRAIN CURRENT (AMPS)
R
DS(on)
LIMIT
THERMAL LIMIT
PACKAGE LIMIT
V
GS
= 10 V
SINGLE PULSE
T
C
= 25°C
1 ms
100 ms
10 ms
dc
10 ms
40
T
J
, JUNCTION TEMPERATURE (°C)
I
D
= 20 A
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
EAS, SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
0
100
200
300
400
0
0
2
4
6
8
51015
1 10 100
10
100
1000
0.70.5
0
10
20
5
15
0.8 0.9
10 100
1
10
100
0.1
1 25 125
20
10
0
75 100 15050
1.0
15
5
700
800
600
500
10
1
0.6
900
1000
50 60
NTD5867NL
http://onsemi.com
5
TYPICAL PERFORMANCE CURVES
Figure 13. Thermal Response
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
(NORMALIZED)
t, TIME (s)
0.1
10
0.01
0.1
0.2
0.02
D = 0.5
0.05
0.01
SINGLE PULSE
R
q
JC
(t) = r(t) R
q
JC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
1
T
J(pk)
− T
C
= P
(pk)
R
q
JC
(t)
P
(pk)
t
1
t
2
DUTY CYCLE, D = t
1
/t
2
0.01 0.10.0010.00010.000010.000001
1.0
ORDERING INFORMATION
Order Number Package Shipping
NTD5867NL−1G IPAK (Straight Lead)
(Pb−Free)
75 Units / Rail
NTD5867NLT4G DPAK
(Pb−Free)
2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NTD5867NL
http://onsemi.com
6
PACKAGE DIMENSIONS
DPAK (SINGLE GUAGE)
CASE 369AA
ISSUE B
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
5.80
0.228
2.58
0.101
1.6
0.063
6.20
0.244
3.0
0.118
6.172
0.243
ǒ
mm
inches
Ǔ
SCALE 3:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
b
D
E
b3
L3
L4
b2
e
M
0.005 (0.13) C
c2
A
c
C
Z
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
D 0.235 0.245 5.97 6.22
E 0.250 0.265 6.35 6.73
A 0.086 0.094 2.18 2.38
b 0.025 0.035 0.63 0.89
c2 0.018 0.024 0.46 0.61
b2 0.030 0.045 0.76 1.14
c 0.018 0.024 0.46 0.61
e 0.090 BSC 2.29 BSC
b3 0.180 0.215 4.57 5.46
L4 −− 0.040 −−− 1.01
L 0.055 0.070 1.40 1.78
L3 0.035 0.050 0.89 1.27
Z 0.155 −− 3.93 −−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-
MENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
12 3
4
H 0.370 0.410 9.40 10.41
A1 0.000 0.005 0.00 0.13
L1 0.108 REF 2.74 REF
L2 0.020 BSC 0.51 BSC
A1
H
DETAIL A
SEATING
PLANE
A
B
C
L1
L
H
L2
GAUGE
PLANE
DETAIL A
ROTATED 90 CW5

NTD5867NLT4G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
MOSFET NFET DPAK 60V 18A 43 MOHM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet