MT9043 Data Sheet
10
Zarlink Semiconductor Inc.
From a reset condition, the MT9043 will take up to 30 seconds (see AC Electrical Characteristics) of input reference
signal to output signals which are synchronized (phase locked) to the reference input.
The selection of input references is control dependent as shown in state table 4. The reference frequencies are
selected by the frequency control pins FS2 and FS1 as shown in Table 1.
Fast Lock Mode
Fast Lock Mode is a submode of Normal Mode, it is used to allow the MT9043 to lock to a reference more quickly
than Normal mode will allow. Typically, the PLL will lock to the incoming reference within 500 ms if the FLOCK pin is
set high.
Freerun Mode
Freerun Mode is typically used when a master clock source is required, or immediately following system power-up
before network synchronization is achieved.
In Freerun Mode, the MT9043 provides timing and synchronization signals which are based on the master clock
frequency (OSCi) only, and are not synchronized to the reference signals (PRI and SEC).
The accuracy of the output clock is equal to the accuracy of the master clock (OSCi). So if a
±32 ppm output clock
is required, the master clock must also be
±32 ppm. See Applications - Crystal and Clock Oscillator sections.
MT9043 Measures of Performance
The following are some synchronizer performance indicators and their corresponding definitions.
Intrinsic Jitter
Intrinsic jitter is the jitter produced by the synchronizing circuit and is measured at its output. It is measured by
applying a reference signal with no jitter to the input of the device, and measuring its output jitter. Intrinsic jitter may
also be measured when the device is free running by measuring the output jitter of the device. Intrinsic jitter is
usually measured with various band limiting filters depending on the applicable standards. In the MT9043, the
intrinsic Jitter is limited to less than 0.02 UI on the 2.048 MHz and 1.544 MHz clocks.
Jitter Tolerance
Jitter tolerance is a measure of the ability of a PLL to operate properly (i.e., remain in lock and or regain lock in the
presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its reference. The applied
jitter magnitude and jitter frequency depends on the applicable standards.
Jitter Transfer
Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter
at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured
with various filters depending on the applicable standards.
For the MT9043, two internal elements determine the jitter attenuation. This includes the internal 1.9 Hz low pass
loop filter and the phase slope limiter. The phase slope limiter limits the output phase slope to 5 ns/125 us.
Therefore, if the input signal exceeds this rate, such as for very large amplitude low frequency input jitter, the
maximum output phase slope will be limited (i.e., attenuated) to 5 ns/125 us.
The MT9043 has twelve outputs with three possible input frequencies (except for 19.44 MHz, which is internally
divided to 8 KHz) for a total of 36 possible jitter transfer functions. Since all outputs are derived from the same
signal, the jitter transfer values for the four cases, 8 kHz to 8 kHz, 1.544 MHz to 1.544 MHz and 2.048 MHz to
2.048 MHz can be applied to all outputs.
