LTC3633
16
3633fd
For more information www.linear.com/LTC3633
APPLICATIONS INFORMATION
Suggested compensation component values are shown in
Figure 3. For a 2MHz application, an R-C network of 220pF
and 13kΩ provides a good starting point. The bandwidth
of the loop increases with decreasing C. If R is increased
by the same factor that C is decreased, the zero frequency
will be kept the same, thereby keeping the phase the same
in the most critical frequency range of the feedback loop.
A 10pF bypass capacitor on the ITH pin is recommended
for the purposes of filtering out high frequency coupling
from stray board capacitance. In addition, a feedforward
capacitor C
F
can be added to improve the high frequency
response, as previously shown in Figure 2. Capacitor C
F
provides phase lead by creating a high frequency zero
with R2 which improves the phase margin.
transient response once the final PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because their various types and values determine the
loop gain and phase. An output current pulse of 20% to
100% of full load current having a rise time of ~1µs will
produce output voltage and ITH pin waveforms that will
give a sense of the overall loop stability without breaking
the feedback loop.
Switching regulators take several cycles to respond to a
step in load current. When a load step occurs, V
OUT
im-
mediately shifts by an amount equal to
∆I
LOAD
• ESR, where
ESR is the effective series resistance of C
OUT
. ∆I
LOAD
also
begins to charge or discharge C
OUT
generating a feedback
error signal used by the regulator to return V
OUT
to its
steady-state value. During this recovery time, V
OUT
can
be monitored for overshoot or ringing that would indicate
a stability problem.
When observing the response of V
OUT
to a load step, the
initial output voltage step may not be within the bandwidth of
the feedback loop, so the standard second order overshoot/
DC ratio cannot be used to determine phase margin. The
output voltage settling behavior is related to the stability
of the closed-loop system and will demonstrate the actual
overall supply performance. For a detailed explanation of
optimizing the compensation components, including a
review of control loop theory, refer to Linear Technology
Application Note 76.
In some applications, a more severe transient can be caused
by switching in loads with large (>10µF) input capacitors.
The discharged input capacitors are effectively put in paral
-
lel with C
OUT
, causing a rapid drop in V
OUT
. No regulator
can deliver enough current to prevent this problem, if
the switch connecting the load has low resistance and is
driven quickly. The solution is to limit the turn-on speed
of the load switch driver. A hot swap controller is designed
specifically for this purpose and usually incorporates cur
-
rent limiting, short-circuit protection, and soft starting.
Checking Transient Response
The regulator loop response can be checked by observing
the response of the system to a load step. When configured
for external compensation, the availability of the ITH pin
not only allows optimization of the control loop behavior
but also provides a DC-coupled and AC filtered closed loop
response test point. The DC step, rise time, and settling
behavior at this test point reflect the closed loop response.
Assuming a predominantly second order system, phase
margin and/or damping factor can be estimated using the
percentage of overshoot seen at this pin.
The ITH external components shown in Figure 3 circuit
will provide an adequate starting point for most applica
-
tions. The series R-C filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.5
to 2 times their suggested values) to optimize
Figure 3. Compensation Component
ITH
R
COMP
13k
C
COMP
220pF
3633 F03
SGND
LTC3633
LTC3633
17
3633fd
For more information www.linear.com/LTC3633
APPLICATIONS INFORMATION
MODE/SYNC Operation
The MODE/SYNC pin is a multipurpose pin allowing both
mode selection and operating frequency synchroniza
-
tion. Floating this pin or connecting it to INTV
CC
enables
Burst Mode operation for superior efficiency at low load
currents at the expense of slightly higher output voltage
ripple. When the MODE/SYNC pin is tied to ground, forced
continuous mode operation is selected, creating the lowest
fixed output ripple at the expense of light load efficiency.
The LTC3633 will detect the presence of the external clock
signal on the MODE/SYNC pin and synchronize the inter
-
nal oscillator to the phase and frequency of the incoming
clock. The presence of an external clock will place both
regulators into for
ced continuous mode operation.
Output V
oltage Tracking and Soft-Start
The LTC3633 allows the user to control the output voltage
ramp rate by means of the TRACKSS pin. From 0 to 0.6V, the
TRACKSS voltage will override the internal 0.6V reference
input to the error amplifier, thus regulating the feedback
voltage to that of the TRACKSS pin. When TRACKSS is
above 0.6V, tracking is disabled and the feedback voltage
will regulate to the internal reference voltage.
The voltage at the TRACKSS pin may be driven from an
external source, or alternatively, the user may leverage
the internal 1.4µA pull-up current source to implement
a soft-start function by connecting an external capacitor
(C
SS
) from the TRACKSS pin to ground. The relationship
between output rise time and TRACKSS capacitance is
given by:
t
SS
= 430000Ω • C
SS
A default internal soft-start ramp forces a minimum soft-
start time of 400µs by overriding the TRACKSS pin input
during this time period. Hence, capacitance values less
than approximately 1000pF will not significantly affect
soft-start behavior.
When driving the TRACKSS pin from another source, each
channel’s output can be set up to either coincidentally or
ratiometrically track another supplys output, as shown in
Figure 4. In the following discussions, V
OUT1
refers to the
LTC3633 output 1 as a master channel and V
OUT2
refers
to output 2 as a slave channel. In practice, either channel
can be used as the master.
To implement the coincident tracking in Figure 4a, con
-
nect an additional resistive divider to V
OUT1
and connect
its midpoint to the TRACKSS pin of the slave channel.
Figure 4. Two Different Modes of Output Voltage Tracking
TIME
(4a) Coincident Tracking
V
OUT1
V
OUT2
OUTPUT VOLTAGE
3633 F04a
V
OUT1
V
OUT2
TIME
3633 F04b
(4b) Ratiometric Tracking
OUTPUT VOLTAGE
LTC3633
18
3633fd
For more information www.linear.com/LTC3633
APPLICATIONS INFORMATION
The ratio of this divider should be the same as that of the
slave channel’s feedback divider shown in Figure 5a. In
this tracking mode, V
OUT1
must be set higher than V
OUT2
.
To implement the ratiometric tracking, the feedback pin of
the master channel should connect to the TRACKSS pin of
the slave channel (as in Figure 5b). By selecting different
resistors, the LTC3633 can achieve different modes of
tracking including the two in Figure 4.
Upon start-up, the regulator defaults to Burst Mode opera
-
tion until the output exceeds 80% of its final value (V
FB
>
0.48V). Once the output reaches this voltage, the operating
mode of the regulator switches to the mode selected by
the MODE/SYNC pin as described above. During normal
operation, if the output drops below 10% of its final value
(as it may when tracking down, for instance), the regulator
will automatically switch to Burst Mode operation to prevent
inductor saturation and improve TRACKSS pin accuracy.
Output Power Good
The PGOOD output of the LTC3633 is driven by a 15Ω
(typical) open-drain pull-down device. This device will be
turned off once the output voltage is within 5% (typical) of
the target regulation point, allowing the voltage at PGOOD
to rise via an external pull-up resistor. If the output voltage
exits an 8% (typical) regulation window around the target
regulation point, the open-drain output will pull down
with 15Ω output resistance to ground, thus dropping the
PGOOD pin voltage. This behavior is described in Figure 6.
A filter time of 40µs (typical) acts to prevent unwanted
PGOOD output changes during V
OUT
transient events.
As a result, the output voltage must be within the target
regulation window of 5% for 40µs before the PGOOD pin
pulls high. Conversely, the output voltage must exit the
8% regulation window for 40µs before the PGOOD pin
pulls to ground.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
Figure 6. PGOOD Pin Behavior
Figure 5. Setup for Coincident and Ratiometric Tracking
PGOOD
VOLTAGE
OUTPUT VOLTAGE
NOMINAL OUTPUT
0% 8%–5% 5%
3633 F06
–8%
R3 R1
R4 R2
R3
V
OUT2
R4
(5a) Coincident Tracking Setup
TO
V
FB1
PIN
TO
TRACKSS2
PIN
TO
V
FB2
PIN
V
OUT1
R1
R2
R3
V
OUT2
R4
3633 F05
(5b) Ratiometric Tracking Setup
TO
V
FB1
PIN
TO
TRACKSS2
PIN
TO
V
FB2
PIN
V
OUT1

LTC3633IFE#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Dual 3A, 15Vin, 4MHz, Monolithic Synchronous Step-Down Regulator
Lifecycle:
New from this manufacturer.
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