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LTC3633IFE#PBF

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LTC3633
19
3633fd
For more information www.linear.com/LTC3633
APPLICATIONS INFORMATION
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
% Efficiency = 100% – (L1 + L2 + L3 +…)
where L1, L2, etc. are the individual losses as a percent
-
age of input power.
Although
all
dissipative elements in the circuit produce
losses, three main sources usually account for most of
the losses in LTC3633 circuits: 1) I
2
R losses, 2) switching
losses and quiescent power loss 3) transition losses and
other losses.
1. I
2
R losses are calculated from the DC resistances of
the internal switches, R
SW
, and external inductor, R
L
.
In continuous mode, the average output current flows
through inductor L but is “chopped” between the
internal top and bottom power MOSFETs. Thus, the
series resistance looking into the SW pin is a function
of both top and bottom MOSFET R
DS(ON)
and the duty
cycle (DC) as follows:
R
SW
= (R
DS(ON)TOP
)(DC) + (R
DS(ON)BOT
)(1 – DC)
The R
DS(ON)
for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
curves. Thus to obtain I
2
R losses:
I
2
R losses = I
OUT
2
(R
SW
+ R
L
)
2. The internal LDO supplies the power to the INTV
CC
rail.
The total power loss here is the sum of the switching
losses and quiescent current losses from the control
circuitry.
Each time a power MOSFET gate is switched from low
to high to low again, a packet of charge dQ moves from
V
IN
to ground. The resulting dQ/dt is a current out of
INTV
CC
that is typically much larger than the DC control
bias current. In continuous mode, I
GATECHG
= f(Q
T
+ Q
B
),
where Q
T
and Q
B
are the gate charges of the internal
top and bottom power MOSFETs and f is the switching
frequency. For estimation purposes, (Q
T
+ Q
B
) on each
LTC3633 regulator channel is approximately 2.3nC.
To calculate the total power loss from the LDO load,
simply add the gate charge current and quiescent cur
-
rent and multiply by V
IN
:
P
LDO
= (I
GATECHG
+ I
Q
) • V
IN
3. Other “hidden” losses such as transition loss, copper
trace resistances, and internal load currents can account
for additional efficiency degradations in the overall power
system. Transition loss arises from the brief amount of
time the top power MOSFET spends in the saturated
region during switch node transitions. The LTC3633
internal power devices switch quickly enough that these
losses are not significant compared to other sources.
Other losses, including diode conduction losses during
dead-time and inductor core losses, generally account
for less than 2% total additional loss.
Thermal Considerations
The LTC3633 requires the exposed package backplane
metal (PGND) to be well soldered to the PC board to
provide good thermal contact. This gives the QFN and
TSSOP packages exceptional thermal properties, which
are necessary to prevent excessive self-heating of the part
in normal operation.
In a majority of applications, the LTC3633 does not dis
-
sipate much heat due to its high efficiency and low thermal
resistance of its exposed-back QFN package. However, in
applications where the L
TC3633 is running at high ambi
-
ent temperature, high V
IN
, high switching frequency, and
maximum output current load, the heat dissipated may
exceed the maximum junction temperature of the part. If
the junction temperature reaches approximately 150°C,
both power switches will be turned off until temperature
returns to 140°C.
To prevent the LTC3633 from exceeding the maximum
junction temperature of 125°C, the user will need to do
some thermal analysis. The goal of the thermal analysis
LTC3633
20
3633fd
For more information www.linear.com/LTC3633
APPLICATIONS INFORMATION
is to determine whether the power dissipated exceeds the
maximum junction temperature of the part. The tempera-
ture rise is given by:
T
RISE
= P
D
• θ
JA
As an example, consider the case when one of the regula-
tors is used in an application where V
IN
= 12V, I
OUT
= 2A,
frequency = 2MHz, V
OUT
= 1.8V. From the R
DS(ON)
graphs
in the Typical Performance Characteristics section, the top
switch on-resistance is nominally 140mΩ and the bottom
switch on-resistance is nominally 80mΩ at 70°C ambient.
The equivalent power MOSFET resistance R
SW
is:
R
DS(ON)
TOP
•
1.8V
12V
+R
DS(ON)
BOT
•
10.2V
12V
= 89mΩ
From the previous section’s discussion on gate drive, we
estimate the total gate drive current through the LDO to be
2MHz • 2.3nC = 4.6mA, and I
Q
of one channel is 0.65mA
(see Electrical Characteristics). Therefore, the total power
dissipated by a single regulator is:
P
D
= I
OUT
2
• R
SW
+ V
IN
• (I
GATECHG
+ I
Q
)
P
D
= (2A)
2
• (0.089Ω) + (12V) • (4.6mA + 0.65mA)
= 0.419W
Running two regulators under the same conditions would
result in a power dissipation of 0.838W. The QFN 5mm
× 4mm package junction-to-ambient thermal resistance,
θ
JA
, is around 43°C/W. Therefore, the junction temperature
of the regulator operating in a 70°C ambient temperature
is approximately:
T
J
= 0.838W • 43°C/W + 70°C = 106°C
which is below the maximum junction temperature of
125°C. With higher ambient temperatures, a heat sink or
cooling fan should be considered to drop the junction-
to-ambient thermal resistance. Alternatively, the TSSOP
package may be a better choice for high power applications,
since it has better thermal properties than the QFN package.
Remembering that the above junction temperature is
obtained from an R
DS(ON)
at 70°C, we might recalculate
the junction temperature based on a higher R
DS(ON)
since
it increases with temperature. Redoing the calculation
assuming that R
SW
increased 12% at 106°C yields a new
junction temperature of 109°C. If the application calls for
a higher ambient temperature and/or higher load currents,
care should be taken to reduce the temperature rise of the
part by using a heat sink or air flow.
Figure 7 is a temperature derating curve based on the
DC1347 demo board (QFN package). It can be used to
estimate the maximum allowable ambient temperature
for given DC load currents in order to avoid exceeding
the maximum operating junction temperature of 125°C.
Junction Temperature Measurement
The junction-to-ambient thermal resistance will vary de
-
pending on the size and amount of heat sinking copper
on the PCB board where the part is mounted, as well as
the amount of air flow on the device. In order to properly
evaluate this thermal resistance, the junction temperature
needs to be measured. A clever way to measure the junc
-
tion temperature directly is to use the internal junction
diode on one of the pins (PGOOD) to measure its diode
voltage change based on ambient temperature change.
First remove any external passive component on the
PGOOD pin, then pull out 100μA from the PGOOD pin to
turn on its internal junction diode and bias the PGOOD
pin to a negative voltage. With no output current load,
measure the PGOOD voltage at an ambient temperature
of 25°C, 75°C and 125°C to establish a slope relationship
between the delta voltage
on PGOOD
and delta ambient
temperature. Once this slope is established, then the
junction temperature rise can be measured as a function
Figure 7. Temperature Derating Curve for DC1347 Demo Circuit
0
CHANNEL 1 LOAD CURRENT (A)
0.5
1.0
1.5
2.0
3.0
2.5
50
125
3633 F07
0
3.5
25 75 100
MAXIMUM ALLOWABLE AMBIENT
TEMPERATURE (°C)
CH2 LOAD = 0A
CH2 LOAD = 1A
CH2 LOAD = 2A
CH2 LOAD = 3A
LTC3633
21
3633fd
For more information www.linear.com/LTC3633
APPLICATIONS INFORMATION
of power loss in the package with corresponding output
load current. Although making this measurement with this
method does violate absolute maximum voltage ratings
on the PGOOD pin, the applied power is so low that there
should be no significant risk of damaging the device.
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3633. Check the following in your layout:
1) Do the input capacitors connect to the V
IN
and PGND
pins as close as possible? These capacitors provide
the AC current to the internal power MOSFETs and their
drivers.
2) The output capacitor, C
OUT
, and inductor L should be
closely connected to minimize loss. The (–) plate of
C
OUT
should be closely connected to both PGND and
the (–) plate of C
IN
.
3) The resistive divider, (e.g. R1 to R4 in Figure 8) must be
connected between the (+) plate of C
OUT
and a ground
line terminated near SGND. The feedback signal V
FB
should be routed away from noisy components and
traces, such as the SW line, and its trace length should
be minimized. In addition, the R
T
resistor and loop
compensation components should be terminated to
SGND.
4) Keep sensitive components away from the SW pin. The
R
T
resistor, the compensation components, the feedback
resistors, and the INTV
CC
bypass capacitor should all
be routed away from the SW trace and the inductor L.
5) A ground plane is preferred, but if not available, the
signal and power grounds should be segregated with
both connecting to a common, low noise reference point.
The connection to the PGND pin should be made with
a minimal resistance trace from the reference point.
6) Flood all unused areas on all layers with copper in order
to reduce the temperature rise of power components.
These copper areas should be connected to the exposed
backside of the package (PGND).
Refer to Figures 9 and 10 for board layout examples.
Design Example
As a design example, consider using the LTC3633 in an
application with the following specifications: V
IN(MAX)
=
13.2V, V
OUT1
= 1.8V, V
OUT2
= 3.3V, I
OUT(MAX)
= 3A, I
OUT(MIN)
= 10mA, f = 2MHz, V
DROOP
~ (5% • V
OUT
). The following
discussion will use equations from the previous sections.
Because efficiency is important at both high and low load
current, Burst Mode operation will be utilized.
First, the correct R
T
resistor value for 2MHz switching fre-
quency must be chosen. Based on the equation discussed
earlier, R
T
should be 160k; the closest standard value is
162k. RT can be tied to INTV
CC
if switching frequency
accuracy is not critical.
Next, determine the channel 1 inductor value for about
40% ripple current at maximum V
IN
:
L1=
1.8V
2MHz • 1.2A
1−
1.8V
13.2V
= 0.64µH
A standard value of 0.68µH should work well here. Solving
the same equation for channel 2 results in a 1µH inductor.
C
OUT
will be selected based on the charge storage require-
ment. For a V
DROOP
of 90mV for a 3A load step:
C
OUT1
≈
3• ∆I
OUT
f
0
V
DROOP
=
3•(3A)
(2MHz)(90mV)
= 50µF
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LTC3633IFE#PBF

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Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Dual 3A, 15Vin, 4MHz, Monolithic Synchronous Step-Down Regulator
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