1/13December 2004
■ HIGH SPEED:
f
MAX
= 170 MHz (TYP.) at V
CC
= 5V
■ LOW POWER DISSIPATION:
I
CC
= 4 µA (MAX.) at T
A
=25°C
■ COMPATIBLE WITH TTL OUTPUTS:
V
IH
= 2V (MIN.), V
IL
= 0.8V (MAX)
■ POWER DOWN PROTECTION ON INPUTS
& OUTPUTS
■ SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8 mA (MIN)
■ BALANCED PROPAGATION DELAYS:
t
PLH
≅ t
PHL
■ OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
■ PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 273
■ IMPROVED LATCH-UP IMMUNITY
■ LOW NOISE: V
OLP
= 0.9V (MAX.)
DESCRIPTION
The 74VHCT273A is an advanced high-speed
CMOS OCTAL D-TYPE FLIP FLOP WITH CLEAR
fabricated with sub-micron silicon gate and
double-layer metal wiring C
2
MOS technology.
Information signals applied to D inputs are
transferred to the Q outputs on the positive going
edge of the clock pulse.
When the CLEAR
input is held low, the Q outputs
are held low independently of the other inputs.
Power down protection is provided on all inputs
and outputs and 0 to 7V can be accepted on
inputs with no regard to the supply voltage. This
device can be used to interface 5V to 3V since all
inputs are equipped with TTL threshold.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74VHCT273A
OCTAL D-TYPE FLIP FLOP WITH CLEAR
Figure 1: Pin Connection And IEC Logic Symbols
Table 1: Order Codes
PACKAGE T & R
SOP 74VHCT273AMTR
TSSOP 74VHCT273ATTR
TSSOPSOP
Rev. 3
