Data Sheet AD8067
Rev. B | Page 11 of 24
FREQUENCY – MHz
OUTPUT IMPEDANCE –
100
0.001
0.01
0.1
1
10
0.01 10 1000.1 1 1000
G = +10
Figure 28. Output Impedance vs. Frequency
I
LOAD
– mA
OUTPUT SATURATION VOLTAGE – V
0.30
0
0.05
0.10
0.15
0.20
0.25
0 5 10 15 20 25 30 35 40
V
CC
– V
OH
V
OL
– V
EE
Figure 29. Output Saturation Voltage vs. Output Load Current
FREQUENCY – MHz
PSRR – dB
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0.01 0.1 1 10 100
–PSRR
+PSRR
Figure 30. PSRR vs. Frequency
TEMPERATURE – °C
QUIESCENT CURRENT – mA
6.7
6.0
6.1
6.2
6.3
6.4
6.5
6.6
–40 –20 0 20 40 60 80
V
S
= ±12V
V
S
= ±5V
V
S
= +5V
Figure 31. Quiescent Current vs. Temperature for Various Supply Voltages
(V
CC
– V
OH
), (V
OL
– V
EE
), V
S
= ±12V
R
L
= 1k
TEMPERATURE – °C
OUTPUT SATURATION VOLTAGE – mV
200
(V
CC
– V
OH
), (V
OL
– V
EE
), V
S
= ±5V
V
OL
– V
EE
, V
S
= +5V
V
CC
– V
OH
, V
S
= +5V
0
20
40
60
80
100
120
140
160
180
–40 –20 0 20 40 60 80
Figure 32. Output Saturation Voltage vs. Temperature
I
LOAD
– mA
OPEN-LOOP GAIN – dB
140
50
60
70
80
90
100
110
120
130
0 5 10 15 20 25 30 35 40
V
S
= ±12V
V
S
= ±5V
V
S
= +5V
Figure 33. Open-Loop Gain vs. Load Current for Various Supplies
AD8067 Data Sheet
Rev. B | Page 12 of 24
TEST CIRCUITS
5
2
3
1
4
AD8067
110
1k
–V
EE
+V
CC
10µF
0.1µF
49.9
10µF
0.1µF
V
OUT
V
IN
+
+
A
V
= 10
R
L
= 1k
Figure 34. Standard Test Circuit
5
2
3
1
4
AD8067
110
100
1k
–V
EE
V
OUT
+V
CC
10µF
0.1µF
10µF
0.1µF
1k
V–
+
+
A
OL
=
V
OUT
V–
Figure 35. Open-Loop Gain Test Circuit
5
2
3
1
4
AD8067
110
1k
–V
EE
+V
CC
10µF
0.1µF
49.9
1k
10µF
0.1µF
C
LOAD
V
OUT
V
IN
R
SNUB
+
+
A
V
= 10
Figure 36. Test Circuit for Capacitive Load
5
2
3
1
4
AD8067
110
1k
V
OUT
–V
EE
+V
CC
10µF
0.1µF
10µF
0.1µF
1k
1k
+
+
110
V
IN
Figure 37. CMRR Test Circuit
5
2
3
1
4
AD8067
110
1k
V
OUT
–V
EE
+V
CC
V
IN
10µF
0.1µF
100
1k
+
Figure 38. Positive PSRR Test Circuit
5
2
3
1
4
AD8067
110
–V
EE
+V
CC
10µF
0.1µF
10µF
0.1µF
NETWORK ANALYZER
1k
+
+
100
V
OUT
Figure 39. Output Impedance Test Circuit
Data Sheet AD8067
Rev. B | Page 13 of 24
THEORY OF OPERATION
The AD8067 is a low noise, wideband, voltage feedback
operational amplifier that combines a precision JFET input
stage with Analog Devices’ dielectrically isolated eXtra Fast
Complementary Bipolar (XFCB) process BJTs. Operating
supply voltages range from 5 V to 24 V. The amplifier features a
patented rail-to-rail output stage capable of driving within
0.25 V of either power supply while sourcing or sinking 30 mA.
The JFET input, composed of N-channel devices, has a
common-mode input range that includes the negative supply
rail and extends to 3 V below the positive supply. In addition,
the potential for phase reversal behavior was eliminated for all
input voltages within the power supplies.
The combination of low noise, dc precision, and high
bandwidth makes the AD8067 uniquely suited for wideband,
very high input impedance, high gain buffer applications. It is
also useful in wideband transimpedance applications, such as a
photodiode interface, that require very low input currents and
dc precision.
BASIC FREQUENCY RESPONSE
The AD8067’s typical open-loop response (see Figure 41) shows
a phase margin of 60° at a gain of +10. Typical configurations
for noninverting and inverting voltage gain applications are
shown in Figure 40 and Figure 42.
The closed-loop frequency response of a basic noninverting
gain configuration can be approximated by:
( )
( )
G
F
G
RR
R
GBPFrequencydBLoop–3Closed
+
×=
DC Gain = R
F
/R
G
+ 1
GBP is the gain bandwidth product of the amplifier. Typical
GBP for the AD8067 is 300 MHz. See Table 5 for the
recommended values for R
G
and R
F
.
1+=
G
F
R
R
GainNoiseionConfiguratngNoninverti
+V
S
AD8067
+
R
X
R
LOAD
+
V
OUT
R
F
FOR BEST PERFORMANCE,
SET R
S
+ R
X
= R
G
|| R
F
10µF0.1µF
10µF
+
0.1µF
R
G
R
S
SIGNAL
SOURCE
–V
S
V
I
+
Figure 40. Noninverting Gain Configuration
FREQUENCY – MHz
GAIN – dB
PHASE – Degrees
90
0
10
20
30
40
50
60
70
80
–10
120
–150
–120
–90
–60
–30
0
30
60
90
–180
0.01 0.1 1 10 100 1000
PHASE
GAIN
Figure 41. Open-Loop Frequency Response
The bandwidth formula only holds true when the phase margin
of the application approaches 90°, which it will in high gain
configurations. The bandwidth of the AD8067 used in a
G = +10 buffer is 54 MHz, considerably faster than the 30 MHz
predicted by the closed loop 3 dB frequency equation. This
extended bandwidth is due to the phase margin being at 60°
instead of 90°. Gains lower than +10 show an increased amount
of peaking, as shown in Figure 4. For gains lower than +7, use
the AD8065, a unity gain stable JFET input op amp with a unity
gain bandwidth of 145 MHz, or refer to the Applications section
for using the AD8067 in a lower gain configuration.
Table 5. Recommended Values of R
G
and R
F
Gain R
G
(Ω) R
F
(kΩ) BW (MHz)
10 110 1 54
20 49.9 1 15
50 20 1 6
100 10 1 3
+V
S
AD8067
+
R
X
R
LOAD
+
V
OUT
R
F
10µF0.1µF
10µF0.1µF
–V
S
R
G
R
S
SIGNAL
SOURCE
V
I
FOR BEST PERFORMANCE, SET R
X
= (R
S
+ R
G
) || R
F
+
+
Figure 42. Inverting Gain Configuration

AD8067ARTZ-REEL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Precision Amplifiers High Gain BW Prec IC
Lifecycle:
New from this manufacturer.
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