3
Commercial Temperature Range
IDT728981 Time Slot Interchange
Digital Switch 128 x 128
Data to be output on the serial streams may come from two sources: Data
Memory or Connection Memory. The Connection Memory is 16 bits wide and
is split into two 8-bit blocks—Connection Memory HIGH and Connection
Memory LOW. Each location in Connection Memory is associated with a
particular channel in an output stream so as to provide a one-to-one correspon-
dence between Connection and Data Memories. This correspondence allows
for per channel control for each TX output stream.
In Processor Mode, data output on the TX is taken from the Connection
Memory Low and originates from the microprocessor (Figure 2). Where as in
Connection Mode (Figure 1), data is read from Data Memory using the address
in Connection Memory. Data destined for a particular channel on the serial
output stream is read during the previous channel time slot to allow time for
memory access and internal parallel-to-serial conversion.
CONNECTION MODE
In Connection Mode, the addresses of input source for all output channels
are stored in the Connection Memory Low. The Connection Memory Low
locations are mapped to corresponding 8-bit x 32-channel output. The contents
of the Data Memory at the selected address are then transferred to the parallel-
to-serial converters. By having the output channel to specify the input channel
through the Connection Memory, input channels can be broadcast to several
output channels.
PROCESSOR MODE
In Processor Mode the CPU writes data to specific Connection Memory Low
locations which are to be output on the TX streams. The contents of the
Connection Memory Low are transferred to the parallel-to-serial converter one
channel before it is to be output and are transmitted each frame to the output until
it is changed by the CPU.
CONTROL
The Connection Memory High bits (Table 4) control the per-channel
functions available in the IDT728981. Output channels are selected into specific
modes such as: Processor mode or Connection mode and Output Drivers
Enabled or in three-state condition.
OUTPUT DRIVE ENABLE (ODE)
The ODE pin is the master three-state output control pin. If the ODE input
is held LOW all TX outputs will be placed in high impedance regardless
Connection Memory High programming. However, if ODE is HIGH, the contents
of Connection Memory High control the output state on a per-channel basis.
DELAY THROUGH THE IDT728981
The transfer of information from the input serial streams to the output serial
streams results in a delay through the device. The delay through the IDT728981
device varies according to the combination of input and output streams and the
movement within the stream from channel to channel. Data received on an input
stream must first be stored in Data Memory before it is sent out.
As information enters the IDT728981 it must first pass through an internal
serial-to-parallel converter. Likewise, before data leaves the device, it must
pass through the internal parallel-to-serial converter. This data preparation has
an effect on the channel positioning in the frame immediately following the
incoming frame—mainly, data cannot leave in the same time slot. Therefore,
information that is to be output in the same channel position as the information
is input, relative to the frame pulse, will be output in the following frame.
Whether information can be output during a following timeslot after the
information entered the IDT728981 depends on which RX stream the channel
information enters on and which TX stream the information leaves on. This is
caused by the order in which input stream information is placed into Data Memory
and the order in which stream information is queued for output. Table 1 shows the
allowable input/output stream combinations for the minimum two channel delay.
5703 drw06
TX
Microprocessor
Receive
Serial Data
Streams
Transmit
Serial Data
Streams
Data
Memory
Connection
Memory
Receive
Serial Data
Streams
5703 drw05
RX TX
Transmit
Serial Data
Streams
Data
Memory
Connection
Memory
Figure 2. Processor Mode
Figure 1. Connection Mode
FUNCTIONAL DESCRIPTION (Cont'd)
Table 1. Input Stream to Output Stream Combinations that can Provide the
Minimum 2-Channel Delay
Input Output Stream
0 1,2,3
13
Table 2. Address Mapping
NOTES:
1. Writing to the Control Register is the only fast transaction.
2. Memory and stream are specified by the contents of the Control Register.
A5 A4 A3 A2 A1 A0 HEX ADDRESS LOCATION
0 X X X 0 0 00-1F Control Register
(1)
100000 20 Channel 0
(2)
100001 21 Channel 1
(2)
1 ••••• • •
· ••••• • •
1 ••••• • •
111111 3F Channel 31
(2)
