9
Commercial Temperature Range
IDT728981 Time Slot Interchange
Digital Switch 128 x 128
CS
DS
5703 drw14
R/W
A5-A0
D7-D0
DTA
t
CSS
t
RWS
t
ADS
t
AKD
t
RDS
t
SWD
t
FWS
t
CSH
t
RWH
t
ADH
t
AKH
t
RDZ
t
DHT
Figure 10. Processor Bus
Symbol Characteristics Min. Typ.
(2)
Max. Unit Test Conditions
t
CSS Chip Select Setup Time 10 0 ⎯ ns
t
RWS Read/Write Setup Time 10 ⎯⎯ ns
t
ADS Address Setup Time 10 ⎯⎯ ns
t
AKD Acknowledgment Delay Fast ⎯ 30 60 ns C
L
= 150pF
t
AKD Acknowledgment Delay Slow 2.7 ⎯ 7.2 cycles C4i cycles
(4)
tFWS Fast Write Data Setup Time 20 ⎯⎯ ns
t
SWD Slow Write Data Delay ⎯ 2.0 1.7 cycles C4i cycles
t
RDS Read Data Setup Time ⎯⎯0.5 cycles C4i cycles, C
L
= 150pF
t
DHT Data Hold Time Read 20 ⎯⎯ ns R
L
= 1KΩ
(3)
, C
L
= 150pF
t
DHT Data Hold Time Write 20 10 ⎯ ns
t
RDZ Read Data to High Impedance ⎯ 30 60 ns R
L
= 1KΩ
(3)
, C
L
= 150pF
t
CSH Chip Select Hold Time 0 ⎯⎯ ns
t
RWH Read/Write Hold Time 0 ⎯⎯ ns
t
ADH Address Hold Time 0 ⎯⎯ ns
t
AKH Acknowledgment Hold Time 10 20 40 ns R
L
= 1KΩ
(3)
, C
L
= 150pF
NOTE:
1. Timing is over recommended temperature and power supply voltages.
2. Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
3. High Impedance is measured by pulling to the appropriate rail with R
L
, with timing corrected to cancel time taken to discharge C
L
.
4. Processor accesses are dependent on the C4i clock, and so some things are expressed as multiples of the C4i.
AC ELECTRICAL CHARACTERISTICS
(1)
⎯ PROCESSOR BUS
