Philips Semiconductors Product data sheet
SC26C562
CMOS dual universal serial communications controller
(CDUSCC)
2006 Aug 10
6
MNEMONIC NAME AND FUNCTIONTYPEPIN
IRQN 6 O Interrupt Request: Active-LOW, open-drain. This output is asserted upon occurrence of any
enabled interrupting condition. The CPU can read the general status register to determine the
interrupting condition(s), or can respond with an interrupt acknowledge cycle to cause the CDUSCC
to output an interrupt vector on the data bus.
IACKN 1 I Interrupt Acknowledge: Active-LOW. When IACKN is asserted, the CDUSCC responds by either
forcing the bus into high-impedance, placing a vector number, call instruction or zero on the data
bus. The vector number can be modified or unmodified by the status. If no interrupt is pending,
IACKN is ignored and the data bus placed in high-impedance.
X1/CLK 47 I Crystal or External Clock: When using the crystal oscillator, the crystal is connected between pins
X1 and X2. If a crystal is not used, an external clock is supplied at this input. This clock is used to
drive the internal bit rate generator, as an optional input to the counter/timer or DPLL, and to provide
other required clocking signals. When a crystal is used, a capacitor must be connected from this pin
to ground.
X2 46 O Crystal 2: Connection for other side of crystal. When a crystal is used, a capacitor must be
connected from this pin to ground. If an external clock is used on X1, this pin should be left floating.
RESETN 25 I Master Reset: Active-LOW. A LOW on this pin resets the transmitters and receivers and resets the
registers shown in Table 1 of the CDUSCC Users’ Guide. Reset is asynchronous, i.e., no clock is
required.
RxDA, RxDB 40, 14 I Channel A (B) Receiver Serial Data Input: The least significant bit is received first. If external
receiver clock is specified for the channel, the input is sampled on the rising edge of the clock.
TxDA, TxDB 39, 15 O Channel A (B) Transmitter Serial Data Output: The least significant bit is transmitted first. This
output is in the marking (HIGH) condition when the transmitter is disabled or when the channel is
operating in local loopback mode. If external transmitter clock is specified for the channel, the data is
shifted on the falling edge of the clock.
RTxCA, RTxCB 43, 11 I/O Channel A (B) Receiver/Transmitter Clock: As an input, it can be programmed to supply the
receiver, transmitter, counter/timer, or DPLL clock. As an output, it can supply the counter/timer
output, the transmitter shift clock (1X), or the receiver sampling clock (1X).
TRxCA, TRxCB 44, 10 I/O Channel A (B) Transmitter/Receiver Clock: As an input, it can supply the receiver, transmitter,
counter/timer, or DPLL clock. As an output, it can supply the counter/timer output, the DPLL output,
the transmitter shift clock (1X), the receiver sampling clock (1X), the transmitter BRG clock (16X),
The receiver BRG clock (16X), or the internal system clock (X1 ÷ 2).
CTSA/BN,
LCA/BN
35, 19 I/O Channel A (B) Clear-to-Send Input or Loop Control Output: Active-LOW. The signal can be pro-
grammed to act as an enable for the transmitter when not in loop mode. The CDUSCC detects logic
level transitions on this input and can be programmed to generate an interrupt when a transition oc-
curs. When operating in the BOP loop mode, this pin becomes a loop control output which is as-
serted and negated by CDUSCC commands. This output provides the means of controlling external
loop interface hardware to go on-line and off-line without disturbing operation of the loop.
DCDA/BN,
SYNIA/BN
42, 12 I Channel A (B) Data Carrier Detected or External Sync Input: The function of this pin is
programmable. As a DCD active-LOW input, it acts as an enable for the receiver or can be used as a
general purpose input. For the DCD function, the CDUSCC detects logic level transitions on this pin
and can be programmed to generate an interrupt when a transition occurs. As an active-LOW
external sync input, it is used in COP mode to obtain character synchronization for the receiver
without receipt of a SYN character. This mode can be used in disc or tape controller applications or
for the optional byte timing lead in X.21.
RTxDRQA/BN,
GPO1A/BN
37, 17 O Channel A (B) Receiver/Transmitter DMA Service Request or General Purpose Output:
Active-LOW. For half-duplex DMA operation, this output indicates to the DMA controller that one or
more characters are available in the receiver FIFO (when the receiver is enabled) or that the transmit
FIFO is not full (when the transmitter is enabled). For full-duplex DMA operation, this output indicates
to the DMA controller that data is available in the receiver FIFO. In non-DMA mode, this pin is a
general purpose output that can be asserted and negated under program control.
TxDRQA/BN,
GPO2A/BN,
RTSA/BN
36, 18 O Channel A (B) Transmitter DMA Service Request, General Purpose Output, or
Request-to-Send: Active-LOW. For full-duplex DMA operation, this output indicates to the DMA
controller that the transmit FIFO is not full and can accept more data. When not in full-duplex DMA
mode, this pin can be programmed as a general purpose or a Request-to-Send output, which can be
asserted and negated under program control.
RTxDAKA/BN,
GPI1A/BN
48, 5 I Channel A (B) Receiver/Transmitter DMA Acknowledge or General Purpose Input: Active-LOW.
For half-duplex single address operation, this input indicates to the CDUSCC that the DMA controller
has acquired the bus and that the requested bus cycle (read receiver FIFO when the receiver is
enabled or load transmitter FIFO when the transmitter is enabled) is beginning. For full-duplex single
address DMA operation, this input indicates to the CDUSCC that the DMA controller has acquired
the bus and that the requested read receiver FIFO bus cycle is beginning. Because the state of this
input can be read under program control, it can be used as a general purpose input when not in
single address DMA mode.
