Philips Semiconductors Product data sheet
SC26C562
CMOS dual universal serial communications controller
(CDUSCC)
2006 Aug 10
8
DC ELECTRICAL CHARACTERISTICS
4,5
T
amb
= 0 °C to +70 °C, V
CC
= 5.0 V ± 10 %
4,5
LIMITS
Min Typ Max
Input LOW voltage:
V
IL
All except X1/CLK – – 0.8 V
X1/CLK – – 0.8 V
Input HIGH voltage except X1/CLK
V
IH
All except X1/CLK 2.0 – – V
X1/CLK 0.8 × V
CC
– V
CC
V
Output LOW voltage:
V
OL
All except IRQN
7
I
OL
= 5.3 mA – – – V
IRQN I
OL
= 8.8 mA – – 0.5 V
V
OH
Output HIGH voltage
(Except open drain outputs)
I
OH
= –400 µA V
CC
– 0.5 – 0.5 V
I
ILX1
X1/CLK input LOW current
10
V
IN
= 0, X2 = open –150 – 0.0 µA
I
IHX1
X1/CLK input HIGH current
10
V
IN
= V
CC
, X2 = GND – – 150 µA
X1 = open, V
IN
= 0 V – – –15 mA
SCX2
u
u
X1 = open, V
IN
= V
CC
– – +15 mA
I
IL
Input LOW current
RESETN, TxDAKN, RxDAKN
V
IN
= 0 V –15 – –0.5 µA
I
I
Input leakage current V
IN
= 0 V to V
CC
–1 – +1 µA
I
OZH
Output off current HIGH, 3-State data bus V
IN
= V
CC
– – +1 µA
I
OZL
Output off current LOW, 3-State data bus V
IN
= 0 V –1 – – µA
I
ODL
Open drain output LOW current in off state:
EOPN, RDYN V
IN
= 0 V –15 – –0.5 µA
IRQN V
IN
= 0 V –1 – – µA
I
ODH
Open drain output HIGH current in off state:
EOPN, IRQN, RDYN V
IN
= V
CC
–1 – 1 µA
I
CC
13
Power supply current
(see Figure 19 for graphs)
– 25 80 mA
C
IN
Input capacitance
9
V
CC
= GND = 0 V – – 10 pF
C
OUT
Output capacitance
9
V
CC
= GND = 0 V – – 15 pF
C
I/O
Input/output capacitance
9
V
CC
= GND = 0 V – – 20 pF
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not
implied.
2. Clock may be stopped (DC) for testing purposes, or when CDUSCC is in non-operational modes.
3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
4. Parameters are valid over specified temperature range.
5. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.2 V and 3.0 V with a
transition time of 20 ns maximum. For X1/CLK, this swing is between 0.2 V and 4.4 V. All time measurements are referenced at input
voltages of 0.2 V and 3.0 V and output voltages of 0.8 V and 2.0 V, as appropriate.
6. See Figure 20 for test conditions for outputs.
7. Tests for open drain outputs are intended to guarantee switching of the output transistor. Measurement of this response is referenced from
midpoint of the switching signal to a point 0.2 V above the actual output signal level. This point represents noise margin that assures true
switching has occurred.
8. Execution of the valid command (after it is latched) requires 3 rising edges of X1 (see Figure 15).
9. These values were not explicitly tested; they are guaranteed by design and characterization data.
10.X1/CLK and X2 are not tested with a crystal installed.
11. X1/CLK frequency must be at least the faster of the receiver or transmitter serial data rate.
12.Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CSN as the ‘strobing’ input. CSN
and RDN (also CSN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle and the signal negated
first terminates the cycle.
13.V
O
= 0 V to V
CC
, Rx and Tx clocks at 10 MHz, X1 clock at 10 MHz.
