4
I+, Current V
EN
= 2.4V Full - - 15 - - 18 mA
I-, Current Full - - 15 - - 18 mA
NOTES:
3. V
DD
/LLS pin = open or grounded for TTL compatibility. V
DD
/LLS pin = V
DD
for CMOS compatibility.
4. At temperatures above 90
o
C, care must be taken to assure V
IN
remains at least 1.0V below the V
SUPPLY
for proper operation.
5. V
IN
= ±10V, I
OUT
= -100µA.
6. V
IN
= 0V, C
L
= 100pF, enable input pulse = 3V, f = 500kHz.
7. C
L
= 40pF, R
L
= 1K, V
EN
= 0.8V, V
IN
= 3V
RMS
, f = 500kHz. Due to the pin to pin capacitance between IN 8/4B and OUT B, channel 8/4B
exhibits 60dB of OFF isolation under the above test conditions.
Electrical Specifications Supplies = +15V, -15V; V
AH
(Logic Level High) = 2.4V, V
AL
(Logic Level Low) = 0.8V; V
DD
/LLS = GND
(Note 3), Unless Otherwise Specified (Continued)
PARAMETER
TEST
CONDITIONS
TEMP
(
o
C)
-8 -5
UNITSMIN TYP MAX MIN TYP MAX
Test Circuits and Waveforms V
DD
/LLS = GND, Unless Otherwise Specified
FIGURE 1. ON RESISTANCE TEST CIRCUIT FIGURE 2. I
D(OFF)
TEST CIRCUIT (NOTE 8)
FIGURE 3. I
S(OFF)
TEST CIRCUIT (NOTE 8) FIGURE 4. I
D(ON)
TEST CIRCUIT (NOTE 8)
FIGURE 5A. MEASUREMENT POINTS FIGURE 5B. TEST CIRCUIT
FIGURE 5. ACCESS TIME
NOTE:
8. Two measurements per channel: ±10V and 10V. (Two measurements per device for I
D(OFF)
±10V and 10V.)
OUT
IN
V
IN
V
2
I
OUT
100µA
r
ON
=
V
2
100µA
±10V
OUT
±10V
EN
0.8V
10V
A
I
D(OFF)
±
OUT
EN
±10V
A
I
S(OFF)
0.8V
10V
±
OUT
±10V
EN
2.4V
10V
A
I
D(ON)
±
A
2
A
0
50%
3.5V
10%
+10V
0V
OUTPUT
-10V
t
A
ADDRESS
DRIVE (V
A
)
±10V
+15V
V+
V-
IN 1
IN 2-7
IN 8
OUTB
A
0
EN
A
1
10
50
kΩ
pF
-15V
A
2
/SDS
50Ω
V
A
2.4V
GND
V
DD
/LLS
10V
±
OUTA
HI-518
