DATA SHEET
Low Voltage, 1:27 Clock Distribution Chip MPC941
MPC941 REVISION 10 3/18/15 1 ©2015 Integrated Device Technology, Inc.
The MPC941 is a 1:27 low voltage clock distribution chip. The device features
the capability to select either a differential LVPECL or an LVCMOS compatible
input. The 27 outputs are LVCMOS compatible and feature the drive strength to
drive 50 series or parallel terminated transmission lines. With output-to-output
skews of 250 ps, the MPC941 is ideal as a clock distribution chip for the most
demanding of synchronous systems. For a similar product with a smaller number
of outputs, please consult the MPC940 data sheet.
LVPECL or LVCMOS Clock Input
250 ps Maximum Output-to-Output Skew
Drives Up to 54 Independent Clock Lines
Maximum Output Frequency of 250 MHz
High Impedance Output Enable
Extended Temperature Range: –40C to +85C
48-Lead LQFP Packaging, Pb-free
3.3 V or 2.5 V V
CC
Supply Voltage
With a low output impedance, in both the HIGH and LOW logic states, the
output buffers of the MPC941 are ideal for driving series terminated transmission
lines. More specifically, each of the 27 MPC941 outputs can drive two series
terminated 50 transmission lines. With this capability, the MPC941 has an effective fanout of 1:54. With this level of fanout, the
MPC941 provides enough copies of low skew clocks for most high performance synchronous systems.
The differential LVPECL inputs of the MPC941 allow the device to interface directly with an LVPECL fanout buffer like the
MC100EP111 to build very wide clock fanout trees or to couple to a high frequency clock source. The LVCMOS input provides a
more standard interface for applications requiring only a single clock distribution chip at relatively low frequencies. In addition,
the two clock sources can be used as a test clock interface as well as the primary system clock. A logic HIGH on the
LVCMOS_CLK_Sel pin will select the LVCMOS level clock input.
The MPC941 is fully 3.3 V and 2.5 V compatible. The 48-lead LQFP package was chosen to optimize performance, board
space and cost of the device. The 48-lead LQFP has a 7x7 mm body size.
LOW VOLTAGE 3.3 V/2.5 V
1:27 CLOCK
DISTRIBUTION CHIP
AE SUFFIX
48-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 932-03
SCALE 2:1
REVISION 10 3/18/15 2 LOW VOLTAGE, 1:27 CLOCK DISTRIBUTION CHIP
MPC941 DATA SHEET
LOGIC DIAGRAM
Table 1. Pin Configuration
Pin I/O Type Function
PECL_CLK,
PECL_CLK
Input LVPECL LVPECL differential reference clock inputs
LVCMOS_CLK Input LVCMOS Alternative reference clock input
LVCMOS_CLK_SEL Input LVCMOS Input reference clock select
OE Input LVCMOS Output tristate control
GND Supply Negative voltage supply output bank (GND)
V
CC
Supply Positive voltage supply
Q0–Q26 Output LVCMOS Clock outputs
Pulldown
0
1
25
Q0
Q1–Q25
Q26
PECL_CLK
PECL_CLK
LVCMOS_CLK
LVCMOS_CLK_SEL
PULLDOWN
OE
Pulldown
Pulldown
Pinout: 48-Lead TQFP (Top View)
FUNCTION TABLE
LVCMOS_CLK_SEL Input
0
1
PECL_CLK
LVCMOS_CLK
V
CC
Q7
Q6
Q5
GND
Q4
Q3
V
CC
Q2
Q1
Q0
GND
GND
Q16
Q17
Q18
V
CC
Q19
Q20
GND
Q21
Q22
Q23
V
CC
GND
Q8
Q9
Q10
V
CC
Q11
Q12
GND
Q13
Q14
Q15
V
CC
Q26
Q25
Q24
GND
37
38
39
40
41
42
43
44
45
46
47
48
23
22
21
20
19
18
17
16
15
14
13
123456789101112
36 35 34 33 32 31 30 29 28 27 26 25
24
MPC941
GND
OE
V
CC
LVCMOS_CLK
LVCMOS_CLKSEL
PECL_CLK
PECL_CLK
V
CC
REVISION 10 3/18/15 3 LOW VOLTAGE, 1:27 CLOCK DISTRIBUTION CHIP
MPC941 DATA SHEET
Table 2. Absolute Maximum Ratings
(1)
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated
conditions is not implied.
Symbol Characteristics Min Max Unit
V
CC
Supply Voltage –0.3 3.6 V
V
IN
DC Input Voltage –0.3 V
CC
+0.3 V
V
OUT
DC Output Voltage –0.3 V
CC
+0.3 V
I
IN
DC Input Current 20 mA
I
OUT
DC Output Current 50 mA
T
S
Storage Temperature –40 125 C
Table 3. DC Characteristics (V
CC
= 3.3 V ± 5%, T
A
= –40 to +85C)
Symbol Characteristics Min Typ Max Unit Condition
V
IH
Input High Voltage LVCMOS_CLK 2.0 V
CC
+ 0.3 V LVCMOS
V
IL
Input Low Voltage LVCMOS_CLK –0.3 0.8 V LVCMOS
I
IN
Input Current 120
(1)
1. Input pull-up / pull-down resistors influence input current.
A
V
PP
Peak-to-Peak Input Voltage PECL_CLK,
PECL_CLK
500 mV LVPECL
V
CMR
Common Mode Range PECL_CLK,
PECL_CLK
1.2 V
CC
–0.8 V LVPECL
V
OH
Output High Voltage 2.4 V I
OH
= –24 mA
(2)
2. The MPC941 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission
line to a termination voltage of V
TT
. Alternatively, the device drives up to two 50 series terminated transmission lines.
V
OL
Output Low Voltage 0.55
0.40
V
V
I
OL
= 24 mA
(2)
I
OL
= 12 mA
I
OZ
Output Tristate Leakage Current 100 A
Z
OUT
Output Impedance 14 – 17
C
PD
Power Dissipation Capacitance 7-8 10 pF Per Output
C
IN
Input Capacitance 4.0 pF
I
CCQ
Maximum Quiescent Supply Current 5 mA All V
CC
Pins
V
TT
Output Termination Voltage V
CC
2 V

MPC941AER2

Mfr. #:
Manufacturer:
IDT
Description:
Clock Drivers & Distribution FSL 1-27 LVCMOS Fanout Buffer
Lifecycle:
New from this manufacturer.
Delivery:
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