Low Skew, 1-to-12 LVCMOS / LVTTL
Clock Multiplier/Zero Delay Buffer
87973
Data Sheet
©2015 Integrated Device Technology, Inc December 7, 20151
PIN ASSIGNMENT
GENERAL DESCRIPTION
The 87973 is a LVCMOS/LVTTL clock generator.
The 87973 has three selectable inputs and provides
fourteen LVCMOS/LVTTL outputs.
The 87973 is a highly fl exible device. The three selectable in-
puts (1 differential and 2 single ended inputs) are often used in
systems requiring redundant clock sources. Up to three
different output frequencies can be generated among the three
output banks.
The three output banks and feedback output each have their
own output dividers which allows the device to generate a
multitude of different bank frequency ratios and output-to-input
frequency ratios. In addition, 2 outputs in Bank C (QC2, QC3)
can be selected to be inverting or non-inverting. The output
frequency range is 8.33MHz to125MHz. The input frequency
range is 5MHz to 120MHz.
The 87973 also has a QSYNC output which can by used for
system synchronization purposes. It monitors Bank A and
Bank C outputs and goes low one period prior to coincident
rising edges of Bank A and Bank C clocks. QSYNC then goes
high again when the coincident rising edges of Bank A and
Bank C occur. This feature is used primarily in applications
where Bank A and Bank C are running at different frequencies,
and is particularly useful when they are running at non-integer
multiples of one another.
Example Applications:
1. System Clock generator: Use a 16.66MHz reference
clock to generate eight 33.33MHz copies for PCI and
four 100MHz copies for the CPU or PCI-X.
2. Line Card Multiplier: Multiply differential 62.5MHz from
a back plane to single-ended 125MHz for the line Card
ASICs and Gigabit Ethernet Serdes.
3. Zero Delay buffer for Synchronous memory: Fan out
up to twelve 100MHz copies from a memory controller
reference clock to the memory chips on a memory mod-
ule with zero delay.
FEATURES
• Fully integrated PLL
• Fourteen LVCMOS/LVTTL outputs; twelve clock outputs,
one feedback, one sync
• Selectable LVCMOS/LVTTL or differential CLK, nCLK inputs
• CLK0, CLK1 can accept the following input levels:
LVCMOS or LVTTL
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Output frequency range: 8.33MHz to 125MHz
• VCO range: 200MHz to 480MHz
• Output skew: 550ps (maximum)
• Cycle-to-cycle jitter: ±100ps (typical)
• Full 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
• Available in lead-free RoHS compliant package
• Compatible with PowerPC™ and Pentium™ Microprocessors
