87973 Data Sheet
©2015 Integrated Device Technology, Inc December 7, 201510
APPLICATION INFORMATION
USING THE OUTPUT FREEZE CIRCUITRY
OVERVIEW
To enable low power states within a system, each output
of 87973 (Except QC0 and QFB) can be individually frozen
(stopped in the logic “0” state) using a simple serial interface
to a 12 bit shift register. A serial interface was chosen to elim-
inate the need for each output to have its own Output Enable
pin, which would dramatically increase pin count and package
cost. Common sources in a system that can be used to drive
the 87973 serial interface are FPGA’s and ASICs.
PROTOCOL
The Serial interface consists of two pins, FRZ_Data (Freeze
Data) and FRZ_CLK (Freeze Clock). Each of the outputs which
can be frozen has its own freeze enable bit in the 12 bit shift
register. The sequence is started by supplying a logic “0” start
bit followed by 12NRZ freeze enable bits. The period of each
FRZ_DATA bit equals the period of the FRZ_CLK signal. The
FRZ_DATA serial transmission should be timed so the 87973 can
sample each FRZ_DATA bit with the rising edge of the FRZ_CLK
signal. To place an output in the freeze state, a logic “0” must be
written to the respective freeze enable bit in the shift register. To
unfreeze an output, a logic “1” must be written to the respective
freeze enable bit. Outputs will not become enabled/disabled until
all 12 data bits are shifted into the shift register. When all 12 data
bits are shifted in the register, the next rising edge of FRZ_CLK
will enable or disable the outputs. If the bit that is following the
12th bit in the register is a logic “0”, it is used for the start bit of
the next cycle; otherwise, the device will wait and won’t start the
next cycle until it sees a logic “0” bit. Freezing and unfreezing of
the output clock is synchronous (see the timing diagram below).
When going into a frozen state, the output clock will go LOW
at the time it would normally go LOW, and the freeze logic will
keep the output low until unfrozen. Likewise, when coming out
of the frozen state, the output will go HIGH only when it would
normally go HIGH. This logic, therefore, prevents runt pulses
when going into and out of the frozen state.
