MAX1185
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
______________________________________________________________________________________ 13
Applications Information
Figure 5 depicts a typical application circuit containing
two single-ended to differential converters. The internal
reference provides a V
DDS
/2 output voltage for level
shifting purposes. The input is buffered and then split
to a voltage follower and inverter. One lowpass filter per
ADC suppresses some of the wideband noise associat-
ed with high-speed operational amplifiers that follows
the amplifiers. The user may select the R
ISO
and C
IN
values to optimize the filter performance, to suit a par-
ticular application. For the application in Figure 5, a
R
ISO
of 50Ω is placed before the capacitive load to
prevent ringing and oscillation. The 22pF C
IN
capacitor
acts as a small bypassing capacitor.
Using Transformer Coupling
An RF transformer (Figure 6) provides an excellent
solution to convert a single-ended source signal to a
fully differential signal, required by the MAX1185 for
optimum performance. Connecting the center tap of the
transformer to COM provides a V
DDS
/2 DC level shift to
the input. Although a 1:1 transformer is shown, a step-
up transformer may be selected to reduce the drive
requirements. A reduced signal swing from the input
driver, such as an op amp, may also improve the over-
all distortion.
In general, the MAX1185 provides better SFDR and
THD with fully differential input signals than single-
ended drive, especially for very high input frequencies.
In differential input mode, even-order harmonics are
lower as both inputs (INA+, INA- and/or INB+, INB-) are
balanced, and each of the ADC inputs only requires
half the signal swing compared to single-ended mode.
t
DOB
t
CL
t
CH
t
CLK
t
DOA
t
DA/B
5 CLOCK-CYCLE LATENCY (CHA), 5.5 CLOCK-CYCLE LATENCY (CHB)
A/B CHB
D0A/B-D9A/B D0B
CHA
D1A
CHB
D1B
CHA
D2A
CHB
D2B
CHA
D3A
CHB
D3B
CHA
D4A
CHB
D4B
CHA
D5A
CHB
D5B
CHA
D6A
CHB
D6B
CHA
CHB
CLK
OUTPUT
D0A/B–D9A/B
OE
t
DISABLE
t
ENABLE
HIGH
IMPEDANCEHIGH IMPEDANCE
VALID DATA
Figure 3. Timing Diagram for Multiplexed Outputs
Figure 4. Output Timing Diagram
MAX1185
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
14 ______________________________________________________________________________________
Table 1. MAX1185 Output Codes For Differential Inputs
*
V
REF
= V
REFP
- V
REFN
DIFFERENTIAL INPUT
VOLTAGE*
DIFFERENTIAL
INPUT
STRAIGHT OFFSET
BINARY
T/B = 0
TWO’S COMPLEMENT
T/B = 1
V
REF
x 511/512 +FULL SCALE - 1LSB 11 1111 1111 01 1111 1111
V
REF
x 1/512 + 1 LSB 10 0000 0001 00 0000 0001
0 Bipolar Zero 10 0000 0000 00 0000 0000
- V
REF
x 1/512 - 1 LSB 01 1111 1111 11 1111 1111
-V
REF
x 511/512 - FULL SCALE + 1 LSB 00 0000 0001 10 0000 0001
-V
REF
x 512/512 - FULL SCALE 00 0000 0000 10 0000 0000
Single-Ended AC-Coupled Input Signal
Figure 7 shows an AC-coupled, single-ended applica-
tion. Amplifiers like the MAX4108 provide high speed,
high bandwidth, low noise, and low distortion to maintain
the integrity of the input signal.
Typical QAM Demodulation Application
The most frequently used modulation technique for digital
communications applications is probably the Quadrature
Amplitude Modulation (QAM). Typically found in spread-
spectrum based systems, a QAM signal represents a
carrier frequency modulated in both amplitude and
phase. At the transmitter, modulating the baseband sig-
nal with quadrature outputs, a local oscillator followed by
subsequent up-conversion can generate the QAM signal.
The result is an in-phase (I) and a quadrature (Q) carrier
component, where the Q component is 90 degree phase-
shifted with respect to the in-phase component. At the
receiver, the QAM signal is divided down into it’s I and Q
components, essentially representing the modulation
process reversed. Figure 8 displays the demodulation
process performed in the analog domain, using the dual
matched 3.3V, 10-bit ADC MAX1185 and the MAX2451
quadrature demodulator to recover and digitize the I and
Q baseband signals. Before being digitized by the
MAX1185, the mixed down-signal components may be fil-
tered by matched analog filters, such as Nyquist or
Pulse-Shaping filters. These remove any unwanted
images from the mixing process, thereby enhancing the
overall signal-to-noise (SNR) performance and minimizing
intersymbol interference.
Grounding, Bypassing, and
Board Layout
The MAX1185 requires high-speed board layout design
techniques. Locate all bypass capacitors as close as
possible to the device, preferably on the same side as
the ADC, using surface-mount devices for minimum
inductance. Bypass V
DD
, REFP, REFN, and COM with
two parallel 0.1µF ceramic capacitors and a 2.2µF
bipolar capacitor to GND. Follow the same rules to
bypass the digital supply (OV
DD
) to OGND. Multilayer
boards with separated ground and power planes pro-
duce the highest level of signal integrity. Consider the
use of a split ground plane arranged to match the
physical location of the analog ground (GND) and the
digital output driver ground (OGND) on the ADC’s
package. The two ground planes should be joined at a
single point such that the noisy digital ground currents
do not interfere with the analog ground plane. The ideal
location of this connection can be determined experi-
mentally at a point along the gap between the two
ground planes, which produces optimum results. Make
this connection with a low-value, surface-mount resistor
(1Ω to 5Ω), a ferrite bead, or a direct short. Alternatively,
all ground pins could share the same ground plane, if
the ground plane is sufficiently isolated from any noisy
digital systems ground plane (e.g., downstream output
buffer or DSP ground plane). Route high-speed digital
signal traces away from the sensitive analog traces of
either channel. Make sure to isolate the analog input
lines to each respective converter to minimize channel-
to-channel crosstalk. Keep all signal lines short and
free of 90 degree turns.
MAX1185
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
______________________________________________________________________________________ 15
Figure 5. Typical Application for Single-Ended-to-Differential Conversion
INPUT
300Ω
-5V
+5V
0.1μF
0.1μF
0.1μF
-5V
600Ω
300Ω
300Ω
INA+
INA-
LOWPASS FILTER
COM
600Ω
+5V
-5V
0.1μF
600Ω
300Ω
600Ω
300Ω
0.1μF
0.1μF
0.1μF
+5V
0.1μF
300Ω
MAX4108
MAX1185
INB+
INB-
MAX4108
MAX4108
LOWPASS FILTER
INPUT
300Ω
-5V
+5V
0.1μF
0.1μF
0.1μF
C
IN
22pF
-5V
600Ω
300Ω
300Ω
LOWPASS FILTER
600Ω
+5V
-5V
0.1μF
600Ω
300Ω
600Ω
300Ω
0.1μF
0.1μF
0.1μF
+5V
0.1μF
300Ω
MAX4108
MAX4108
MAX4108
300Ω
LOWPASS FILTER
R
IS0
50Ω
C
IN
22pF
R
IS0
50Ω
C
IN
22pF
R
IS0
50Ω
C
IN
22pF
R
IS0
50Ω

MAX1185ECM+TD

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC 10-Bit 2Ch 20Msps High Speed ADC
Lifecycle:
New from this manufacturer.
Delivery:
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