1. Description
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32
registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to
be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code
efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The ATmega64A provides the following features: 64 Kbytes In-System Programmable Flash with Read-
While- Write capabilities, 2 Kbytes EEPROM, 4 Kbytes SRAM, 53 general purpose I/O lines, 32 general
purpose working registers, Real Time Counter (RTC), four flexible Timer/Counters with compare modes
and PWM, two USARTs, a byte oriented Two-wire Serial Interface, an 8-channel, 10-bit ADC with optional
differential input stage with programmable gain, programmable Watchdog Timer with internal Oscillator,
an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip
Debug system and programming, and six software selectable power saving modes. The Idle mode stops
the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue
functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all
other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous
timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping.
The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and
ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator
Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with
low power consumption. In Extended Standby mode, both the main Oscillator and the asynchronous timer
continue to run.
The device is manufactured using Atmel’s high-density non-volatile memory technology. The On-chip ISP
Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a
conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core.
The Boot Program can use any interface to download the Application Program in the Application Flash
memory. Software in the Boot Flash section will continue to run while the Application Flash section is
updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System
Self-Programmable Flash on a monolithic chip, the Atmel ATmega64A is a powerful microcontroller that
provides a highly-flexible and cost-effective solution to many embedded control applications.
The ATmega64A AVR is supported with a full suite of program and system development tools including: C
compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.
Atmel ATmega64A [DATASHEET]
Atmel-8160ES-8-bit AVR Micrcontroller_Datasheet_Summary-09/2015
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