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MAX1246ACEE

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
MAX1246/MAX1247
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +2.7V to +3.6V (MAX1246); V
DD
= +2.7V to +5.25V (MAX1247); COM = 0V; f
SCLK
= 2.0MHz; external clock (50% duty cycle);
15 clocks/conversion cycle (133ksps); MAX1246—4.7µF capacitor at VREF pin; MAX1247—external reference, VREF = 2.5V applied
to VREF pin; T
A
= T
MIN
to T
MAX
; unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
EXTERNAL REFERENCE AT REFADJ
Internal compensation mode 0
Capacitive Bypass at VREF
External compensation mode 4.7
µF
MAX1246
2.06
Reference Buffer Gain
MAX1247
2.00
V/V
MAX1246
±50
REFADJ Input Current
MAX1247
±10
µA
MAX1246/MAX1247
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +2.7V to +3.6V (MAX1246); V
DD
= +2.7V to +5.25V (MAX1247); COM = 0V; f
SCLK
= 2.0MHz; external clock (50% duty cycle);
15 clocks/conversion cycle (133ksps); MAX1246—4.7µF capacitor at VREF pin; MAX1247—external reference, VREF = 2.5V applied
to VREF pin; T
A
= T
MIN
to T
MAX
; unless otherwise noted.)
V
3.0
V
IH
V
DD
= 3.6V
DIN, SCLK, CS Input High Voltage
V
DD
> 3.6V, MAX1247 only
mV±0.3PSRSupply Rejection (Note 10)
V
DD
= 2.7V to V
DD(MAX)
, full-scale input,
external reference = 2.500V
pF15C
IN
DIN, SCLK, CS Input Capacitance
µA±0.01 ±1I
IN
DIN, SCLK, CS Input Leakage
V0.2V
HYST
DIN, SCLK, CS Input Hysteresis
V0.8V
IL
DIN, SCLK, CS Input Low Voltage
2.0
µA±4.0I
S
SHDN Input Current
V0.4V
SL
SHDN Input Low Voltage
VV
DD
- 0.4V
SH
SHDN Input High Voltage
SHDN = 0V or V
DD
nA±100
SHDN Maximum Allowed
Leakage, Mid Input
VV
DD
/ 2V
FLT
SHDN Voltage, Floating
SHDN = FLOAT
SHDN = FLOAT
UNITSMIN TYP MAXSYMBOLPARAMETER
(Note 7)
V
IN
= 0V or V
DD
V
DD
≤ 3.6V
I
DD
CONDITIONS
Positive Supply Current, MAX1246
µA
1.2 2.0
µA±0.01 ±10I
L
Three-State Leakage Current
VV
DD
- 0.5V
OH
Output Voltage High
V
0.8
V
OL
Output Voltage Low
0.4
2.70 3.60
pF15C
OUT
Three-State Output Capacitance
MAX1246
CS = V
DD
(Note 7)
CS = V
DD
I
SOURCE
= 0.5mA
I
SINK
= 16mA
I
SINK
= 5mA
V
2.70 5.25
V
DD
Positive Supply Voltage
MAX1247
0.9 1.5
Operating mode,
full-scale input
30 70
V
DD
= 5.25V
V
DD
= 3.6V
3.5 15V
DD
= 5.25V
V
DD
= 3.6V 1.2 10
Full power-down
mA
1.8 2.5
30 70
1.2 10
Operating mode, full-scale input
Fast power-down
Full power-down
mA
V1.1 V
DD
- 1.1V
SM
SHDN Input Mid Voltage
Fast power-downI
DD
µA
Positive Supply Current, MAX1247
DIGITAL INPUTS (DIN, SCLK, CS, SHDN)
DIGITAL OUTPUTS (DOUT, SSTRB)
POWER REQUIREMENTS
MAX1246/MAX1247
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
6 _______________________________________________________________________________________
__________________________________________Typical Operating Characteristics
(V
DD
= 3V, VREF = 2.5V, f
SCLK
= 2MHz, C
LOAD
= 20pF, T
A
= +25°C, unless otherwise noted.)
0.5
0 1024 2048 3072 4096
INTEGRAL NONLINEARITY
vs. CODE
0.3
-0.3
-0.5
-0.1
0.1
0.4
0.2
-0.4
-0.2
0
MAX1247-01
CODE
INL (LSB)
0.50
0.00
2.25 2.75 4.25
INTEGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
V
DD
(V)
INL (LSB)
3.75 5.253.25 4.75
MAX1247-02
MAX1246
MAX1247
0.00
0.10
0.20
0.30
0.40
0.50
0.05
0.15
0.25
0.35
0.45
-60 -20 20 60 100 140
INTEGRAL NONLINEARITY
vs. TEMPERATURE
TEMPERATURE
(°C)
INL (LSB)
MAX1247-03
MAX1247
MAX1246
V
DD
= 2.7V
TIMING CHARACTERISTICS
(V
DD
= +2.7V to +3.6V (MAX1246); V
DD
= +2.7V to +5.25V (MAX1247); T
A
= T
MIN
to T
MAX
; unless otherwise noted.)
Note 1: Tested at V
DD
= 2.7V; COM = 0V; unipolar single-ended input mode.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: MAX1246—internal reference, offset nulled; MAX1247—external reference (V
REF
= +2.500V), offset nulled.
Note 4: Ground “on” channel; sine wave applied to all “off” channels.
Note 5: Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6: The common-mode range for the analog inputs is from AGND to V
DD
.
Note 7: Guaranteed by design. Not subject to production testing.
Note 8: External load should not change during conversion for specified accuracy.
Note 9: ADC performance is limited by the converter’s noise floor, typically 300µVp-p.
Note
10:
Measured as
|
V
FS
(2.7V) - V
FS
(V
DD.MAX
)
|
.
Internal clock mode only (Note 7)
External clock mode only, Figure 2
External clock mode only, Figure 1
DIN to SCLK Setup
Figure 1
Figure 2
Figure 1
MAX124_ _C/E
CONDITIONS
MAX124_ _M
ns
20 240
Figure 1
ns
t
CSH
ns240t
STR
CS Rise to SSTRB Output Disable
ns240t
SDV
CS Fall to SSTRB Output Enable
240t
SSTRB
SCLK Fall to SSTRB ns
200t
CL
SCLK Pulse Width Low
ns200SCLK Pulse Width High
ns0
CS to SCLK Rise Hold
ns100t
CSS
CS to SCLK Rise Setup
ns240t
TR
CS Rise to Output Disable
ns240t
DV
CS Fall to Output Enable
t
CH
20 200
t
DO
SCLK Fall to Output Data Valid
ns0t
DH
DIN to SCLK Hold
ns
µs1.5t
ACQ
Acquisition Time
0t
SCK
SSTRB Rise to SCLK Rise
ns100t
DS
UNITSMIN TYP MAXSYMBOLPARAMETER
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

MAX1246ACEE

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Buy MAX1246ACEE
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Description:
IC ADC LP 12-BIT SERIAL 16-QSOP
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New from this manufacturer.
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