ADuM3400/ADuM3401/ADuM3402 Data Sheet
Rev. E | Page 10 of 24
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
BRW Package
Minimum Pulse Width
2
PW 100 ns C
L
= 15 pF, CMOS signal levels
Maximum Data Rate
3
10 Mbps C
L
= 15 pF, CMOS signal levels
Propagation Delay
4
t
PHL
, t
PLH
15 35 50 ns C
L
= 15 pF, CMOS signal levels
Pulse Width Distortion, |t
PLH
− t
PHL
|
4
PWD
3
ns
C
L
= 15 pF, CMOS signal levels
Change vs. Temperature 5 ps/°C C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew
5
t
PSK
22 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Codirectional Channels
6
t
PSKCD
3 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Opposing-Directional Channels
6
t
PSKOD
6 ns C
L
= 15 pF, CMOS signal levels
CRW Package
Minimum Pulse Width
2
PW 8.3 11.1 ns C
L
= 15 pF, CMOS signal levels
Maximum Data Rate
3
90 120 Mbps C
L
= 15 pF, CMOS signal levels
Propagation Delay
4
t
PHL
, t
PLH
20 30 40 ns C
L
= 15 pF, CMOS signal levels
Pulse Width Distortion, |t
PLH
− t
PHL
|
4
PWD 0.5 2 ns C
L
= 15 pF, CMOS signal levels
Change vs. Temperature 3 ps/°C C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew
5
t
PSK
14 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Codirectional Channels
6
t
PSKCD
2 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Opposing-Directional Channels
6
t
PSKOD
5 ns C
L
= 15 pF, CMOS signal levels
For All Models
Output Disable Propagation Delay
(High/Low-to-High Impedance)
t
PHZ
, t
PLH
6 8 ns C
L
= 15 pF, CMOS signal levels
Output Enable Propagation Delay
(High Impedance-to-High/Low)
t
PZH
, t
PZL
6 8 ns C
L
= 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%) t
R
/t
f
C
L
= 15 pF, CMOS signal levels
5 V/3.3 V Operation 3.0 ns
3.3 V/5 V Operation 2.5 ns
Common-Mode Transient Immunity
at Logic High Output
7
|CM
H
| 25 35 kV/µs V
Ix
= V
DD1
/V
DD2
, V
CM
= 1000 V,
transient magnitude = 800 V
Common-Mode Transient Immunity
at Logic Low Output
7
|CM
L
|
25
35
kV/µs
V
Ix
= 0 V, V
CM
= 1000 V,
transient magnitude = 800 V
Data Sheet ADuM3400/ADuM3401/ADuM3402
Rev. E | Page 11 of 24
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Refresh Rate f
r
5 V/3.3 V Operation 1.2 Mbps
3.3 V/5 V Operation 1.1 Mbps
Input Dynamic Supply Current per Channel
8
I
DDI (D)
5 V/3.3 V Operation
0.20
mA/Mbps
3.3 V/5 V Operation 0.10 mA/Mbps
Output Dynamic Supply Current per Channel
8
I
DDO (D)
5 V/3.3 V Operation 0.03 mA/Mbps
3.3 V/5 V Operation 0.05 mA/Mbps
1
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total V
DD1
and V
DD2
supply currents as a function of data rate for ADuM3400/ADuM3401/ADuM3402 channel configurations.
2
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4
t
PHL
propagation delay is measured from the 50% level of the falling edge of the V
Ix
signal to the 50% level of the falling edge of the V
Ox
signal. t
PLH
propagation delay is
measured from the 50% level of the rising edge of the V
Ix
signal to the 50% level of the rising edge of the V
Ox
signal.
5
t
PSK
is the magnitude of the worst-case difference in t
PHL
or t
PLH
that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
6
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7
CM
H
is the maximum common-mode voltage slew rate that can be sustained while maintaining V
O
> 0.8 V
DD2
. CM
L
is the maximum common-mode voltage slew rate
that can be sustained while maintaining V
O
< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
ADuM3400/ADuM3401/ADuM3402 Data Sheet
Rev. E | Page 12 of 24
PACKAGE CHARACTERISTICS
Table 4.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Resistance (Input-to-Output)
1
R
I-O
10
12
Capacitance (Input-to-Output)
1
C
I-O
2.2 pF f = 1 MHz
Input Capacitance
2
C
I
4.0 pF
IC Junction-to-Case Thermal Resistance, Side 1 θ
JCI
33 °C/W Thermocouple located at
center of package underside
IC Junction-to-Case Thermal Resistance, Side 2 θ
JCO
28 °C/W
1
Device considered a 2-terminal device; Pin 1 to Pin 8 are shorted together and Pin 9 to Pin 16 are shorted together.
2
Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
The ADuM3400/ADuM3401/ADuM3402 are approved by the organizations listed in Table 5. Refer to Table 10 and the Insulation
Lifetime section for details regarding recommended maximum working voltages for specific cross-isolation waveforms and insulation
levels.
Table 5.
UL CSA CQC VDE
Recognized
Under 1577
Component
Recognition
Program
1
Approved under CSA Component
Acceptance Notice 5A
Approved under
CQC11-471543-2012
Certified according to
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12
2
Single Protection,
2500 V rms Isolation
Voltage
Basic insulation per
CSA 60950-1-03 and IEC 60950-1,
800 V rms (1131 V peak)
maximum working voltage
Basic insulation per
GB4943.1-2011 400 V rms
(588 V peak) maximum
working voltage, tropical
climate, altitude ≤
5000 meters
Reinforced insulation, 560 V peak
Reinforced insulation per
CSA 60950-1-03 and IEC 60950-1,
400 V rms (566 V peak) maximum
working voltage
File E214100 File 205078 File CQC14001117249 File 2471900-4880-0001
1
In accordance with UL 1577, each ADuM3400/ADuM3401/ADuM3402 is proof tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage
detection limit = 5 µA).
2
In accordance with DIN V VDE V 0884-10, each ADuM3400/ADuM3401/ADuM3402 is proof tested by applying an insulation test voltage ≥1050 V peak for 1 sec (partial
discharge detection limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10
approval.
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 6.
Parameter Symbol Value Unit Conditions
Rated Dielectric Insulation Voltage 2500 V rms 1-minute duration
Minimum External Air Gap (Clearance) L(I01) 7.7 min mm Measured from input terminals to output terminals,
shortest distance through air
Minimum External Tracking (Creepage) L(I02) 8.1 min mm Measured from input terminals to output terminals,
shortest distance path along body
Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >400 V DIN IEC 112/VDE 0303 Part 1
Isolation Group II Material Group (DIN VDE 0110, 1/89, Table 1)

ADUM3400ARWZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital Isolators Quad-CH Digital EH System-Level ESD
Lifecycle:
New from this manufacturer.
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