SiC638
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Vishay Siliconix
S18-0299-Rev. A, 19-Mar-18
5
Document Number: 76582
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Notes
(1)
Typical limits are established by characterization and are not production tested
(2)
Guaranteed by design
DETAILED OPERATIONAL DESCRIPTION
PWM Input with Tri-state Function
The PWM input receives the PWM control signal from the VR
controller IC. The PWM input is designed to be compatible
with standard controllers using two state logic (H and L) and
advanced controllers that incorporate tri-state logic (H, L
and tri-state) on the PWM output. For two state logic, the
PWM input operates as follows. When PWM is driven above
V
PWM_TH_R
the low side is turned OFF and the high side is
turned ON. When PWM input is driven below V
PWM_TH_F
the
high side is turned OFF and the low side is turned ON. For
tri-state logic, the PWM input operates as previously stated
for driving the MOSFETs when PWM is logic high and logic
low. However, there is a third state that is entered as the
PWM output of tri-state compatible controller enters its high
impedance state during shut-down. The high impedance
state of the controller’s PWM output allows the SiC638 and
SiC638A to pull the PWM input into the tri-state region (see
definition of PWM logic and Tri-State, fig. 4). If the PWM
input stays in this region for the Tri-state Hold-Off Period,
tTSHO, both high side and low side MOSFETs are turned
OFF. The function allows the VR phase to be disabled
without negative output voltage swing caused by inductor
ringing and saves a Schottky diode clamp. The PWM and
tri-state regions are separated by hysteresis to prevent false
triggering. The SiC638A incorporates PWM voltage
thresholds that are compatible with 3.3 V logic and the
SiC638 thresholds are compatible with 5 V logic.
Disable (DSBL#)
In the low state, the DSBL# pin shuts down the driver IC and
disables both high side and low side MOSFETs. In this state,
standby current is minimized. If DSBL# is left unconnected,
an internal pull-down resistor will pull the pin to C
GND
and
shut down the IC.
Diode Emulation Mode (ZCD_EN#)
When ZCD_EN# pin is driven below V
IL_ZCD_EN#
. diode
emulation mode is enabled. If the PWM signal switches
below V
TH_PWM_F
then the LS MOSFET is under control of
the ZCD (zero crossing detect) comparator. If, after the
internal blanking delay, the inductor current becomes less
than or = 0 the low side is turned OFF. Light load efficiency
is improved by avoiding discharge of output capacitors. If
both high side and low side MOSFETs are required to be
turned OFF, regardless of inductor current, the PWM input
should be tri-stated.
Thermal Shutdown Warning (THWn)
The THWn pin is an open drain signal that flags the presence
of excessive junction temperature. Connect with a
maximum of 20 k, to V
CIN
. An internal temperature sensor
detects the junction temperature. The temperature
threshold is 160 °C. When this junction temperature is
exceeded the THWn flag is set. When the junction
temperature drops below 135 °C the device will clear the
THWn signal. The SiC638 and SiC638A do not stop
operation when the flag is set. The decision to shutdown
must be made by an external thermal control function.
Voltage Input (V
IN
)
This is the power input to the drain of the high side power
MOSFET. This pin is connected to the high power
intermediate BUS rail.
DSBL# ZCD_EN# INPUT
DSBL# logic input voltage
V
IH_DSBL#
Input logic high 2 - -
V
V
IL_DSBL#
Input logic low - - 0.8
ZCD_EN# logic input voltage
V
IH_ZCD_EN#
Input logic high 2 - -
V
IL_ZCD_EN#
Input logic low - - 0.8
PROTECTION
Under voltage lockout V
UVLO
V
CIN
rising, on threshold - 3.7 4.1
V
V
CIN
falling, off threshold 2.7 3.1 -
Under voltage lockout hysteresis V
UVLO_HYST
- 575 - mV
THWn flag set
(2)
T
THWn_SET
- 160 -
°CTHWn flag clear
(2)
T
THWn_CLEAR
- 135 -
THWn flag hysteresis
(2)
T
THWn_HYST
-25-
THWn output low V
OL_THWn
I
THWn
= 2 mA - 0.02 - V
ELECTRICAL SPECIFICATIONS
(DSBL# = ZCD_EN# = 5 V, V
IN
= 12 V, V
DRV
and V
CIN
= 5 V, T
A
= 25 °C)
PARAMETER SYMBOL TEST CONDITION
LIMITS
UNIT
MIN. TYP. MAX.
