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MP1492DS-LF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
MP1492 – 2A, 4.2V-16V INPUT, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
MP1492 Rev. 1.1 www.MonolithicPower.com 13
3/13/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
APPLICATION INFORMATION
Setting the Output Voltage-Large ESR Caps
For applications that electrolytic capacitor or POS
capacitor with a controlled output of ESR is set
as output capacitors. The output voltage is set by
feedback resistors R1 and R2. As figure 8 shows.
Figure 8—Simplified Circuit of POS Capacitor
First, choose a value for R2. R2 should be
chosen reasonably, a small R2 will lead to
considerable quiescent current loss while too
large R2 makes the FB noise sensitive. It is
recommended to choose a value within 5k-
50k for R2, using a comparatively larger R2
when Vo is low,etc.,1.05V, and a smaller R2
when Vo is high. Then R1 is determined as follow
with the output ripple considered:
OUT OUT REF
12
REF
1
VVV
2
RR
V
−Δ −
=
(10)
OUT
VΔ is the output ripple determined by equation
19.
Figure 9—Simplified Circuit of Ceramic
Capacitor
Setting the Output Voltage-Small ESR Caps
When low ESR ceramic capacitor is used in the
output, an external voltage ramp should be
added to FB through resistor R4 and capacitor
C4.The output voltage is influenced by ramp
voltage V
RAMP
besides R divider. The V
RAMP
can
be calculated as shown in equation 6, R2 should
be chosen reasonably, a small R2 will lead to
considerable quiescent current loss while too
large R2 makes the FB noise sensitive. It is
recommended to choose a value within 5k-
50k for R2, using a comparatively larger R2
when Vo is low, etc.,1.05V, and a smaller R2
when Vo is high. And the value of R1 then is
determined as follow:
2
1
FB(AVG)
2
OUT FB(AVG) 4 9
R
R=
V
R
-
(V -V ) R +R
(11)
The V
FB(AVG)
is the average value on the FB,
V
FB(AVG)
varies with the Vin, Vo, and load
condition, etc., its value on the skip mode would
be lower than that of the PWM mode, which
means the load regulation is strictly related to the
V
FB(AVG)
. Also the line regulation is related to the
V
FB(AVG)
,if one wants to gets a better load or line
regulation, a lower Vramp is suggested once it
meets equation 8.
For PWM operation, V
FB(AVG)
value can be
deduced from equation 12.
12
FB( AVG) REF RAMP
12 9
R//R
1
VVV
2R//RR
=+ ×
+
(12)
Usually, R9 is set to 0, and it can also be set
following equation 13 for a better noise immunity.
It should also set to be 5 timers smaller than
R1//R2 to minimize its influence on Vramp.
9
4SW
1
R
2C2F
≤
π× ×
(13)
Using equation 11 to calculate the output voltage
can be complicated. To simplify the calculation of
R1 in equation 11, a DC-blocking capacitor Cdc
can be added to filter the DC influence from R4
and R9. Figure 10 shows a simplified circuit with
external ramp compensation and a DC-blocking
capacitor. With this capacitor, R1 can easily be
obtained by using equation 14 for PWM mode
operation.
−−
=
+
OUT REF RAMP
12
REF RAMP
1
(V V V )
2
RR
1
VV
2
(14)
Cdc is suggested to be at least 10 times larger
than C4 for better DC blocking performance, and
MP1492 – 2A, 4.2V-16V INPUT, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
MP1492 Rev. 1.1 www.MonolithicPower.com 14
3/13/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
should also not larger than 0.47F considering
start up performance. In case one wants to use a
larger Cdc for a better FB noise immunity,
combined with reducing R1 and R2 to limit the
Cdc in a reasonable value without affecting the
system start up. Be noted that even when the
Cdc is applied, the load and line regulation are
still Vramp related.
Figure10—Simplified Circuit of Ceramic
Capacitor with DC blocking capacitor
Input Capacitor
The input current to the step-down converter is
discontinuous, therefore a capacitor is required to
supply the AC current to the step-down converter
while maintaining the DC input voltage. Ceramic
capacitors are recommended for best
performance. In the layout, it’s recommended to
put the input capacitor as close as possible to the
VIN pin.
The capacitance varies significantly over
temperature. Capacitors with X5R and X7R
ceramic dielectrics are recommended because
they are fairly stable over temperature.
The capacitors must also have a ripple current
rating greater than the maximum input ripple
current of the converter. The input ripple current
can be estimated as follows:
OUT OUT
CIN OUT
IN IN
VV
II (1 )
VV
=× ×−
(15)
The worst-case condition occurs at V
IN
= 2V
OUT
,
where:
OUT
CIN
I
I
2
=
(16)
For simplification, choose the input capacitor
whose RMS current rating is greater than half of
the maximum load current.
The input capacitance value determines the input
voltage ripple of the converter. If there is an input
voltage ripple requirement in the system design,
choose the input capacitor that meets the
specification.The input voltage ripple can be
estimated as follows:
OUT OUT OUT
IN
SIN IN IN
IV V
V(1)
FC V V
Δ= × ×−
×
(17)
The worst-case condition occurs at V
IN
= 2V
OUT
,
where:
OUT
IN
SIN
I
1
V
4F C
Δ=×
×
(18)
Output Capacitor
The output capacitor is required to maintain the
DC output voltage. Ceramic or POSCAP
capacitors are recommended. The output voltage
ripple can be estimated as:
OUT OUT
OUT ESR
SW IN SW OUT
VV
1
V(1)(R )
FL V 8FC
Δ= ×− × +
×××
(19)
In the case of ceramic capacitors, the impedance
at the switching frequency is dominated by the
capacitance. The output voltage ripple is mainly
caused by the capacitance. For simplification, the
output voltage ripple can be estimated by:
OUT OUT
OUT
2
SOUT IN
VV
V(1)
8F LC V
Δ= ×−
×××
(20)
The output voltage ripple caused by ESR is very
small. Therefore, an external ramp is needed to
stabilize the system. The external ramp can be
generated through resistor R4 and capacitor C4
following equation 4, 7 and 8.
In the case of POSCAP or electrolytic capacitors,
the ESR dominates the impedance at the
switching frequency. The ramp voltage generated
from the ESR is high enough to stabilize the
system. So the external ramp is not
recommended. A minimum ESR value of 12m
is required to ensure stable operation of the
converter. For simplification, the output ripple can
be approximated to:
OUT OUT
OUT ESR
SIN
VV
V(1)R
FL V
Δ= ×− ×
×
(21)
MP1492 – 2A, 4.2V-16V INPUT, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
MP1492 Rev. 1.1 www.MonolithicPower.com 15
3/13/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
Maximum output capacitor limitation should be
also considered in design application. MP1492
has an around 1ms soft-start time period. If the
output capacitor value is too high, the output
voltage can’t reach the design value during the
soft-start time, and then it will fail to regulate. The
maximum output capacitor value C
o_max
can be
limited approximately by:
O_MAX LIM_AVG OUT ss OUT
C(I I)T/V=−× (22)
Where, I
LIM_AVG
is the average start-up current
during soft-start period. T
ss
is the soft-start time.
Inductor
The inductor is required to supply constant
current to the output load while being driven by
the switched input voltage. A larger value
inductor will result in less ripple current that will
result in lower output ripple voltage. However, the
larger value inductor will have a larger physical
size, higher series resistance, and/or lower
saturation current. A good rule of thumb for
determining the inductance to use is to allow the
peak-to-peak ripple current in the inductor to be
approximately 30~40% of the maximum switch
current limit. Also, make sure that the peak
inductor current is below the maximum switch
current limit. The inductance value can be
calculated by:
OUT OUT
SL IN
VV
L(1)
FI V
=×−
×Δ
(23)
Where I
L
is the peak-to-peak inductor ripple
current.
Choose an inductor that will not saturate under
the maximum inductor peak current. The peak
inductor current can be calculated by:
OUT OUT
LP OUT
SIN
VV
II (1 )
2F L V
=+ ×−
×
(24)
Application Recommendation
As Figure 8 shows, when output cap is
electrolytic POSCAP, etc with large ESR, no
external ramp is needed. Recommended
parameters are listed below in Table 1 to Table 3
Table 1—300kHz Recommended Parameters
without External Ramp Compensation
Recommended Conditions: V
IN
=12V, I
OUT
=2A
V
OUT
(V)
L
(μH)
R1
(kΩ)
R2
(kΩ)
R7
(kΩ)
1.2 3.3 12.1 26.1 402
2.5 3.3 30 14.3 820
3.3 3.3 40.2 13.3 1000
Table 2—500kHz Recommended Parameters
without External Ramp Compensation
Recommended Conditions: V
IN
=12V, I
OUT
=2A
V
OUT
(V)
L
(μH)
R1
(kΩ)
R2
(kΩ)
R7
(kΩ)
1.2 3.3 12.1 26.1 240
2.5 3.3 30 14.3 510
3.3 3.3 40.2 13.3 649
Table 3—700kHz Recommended Parameters
without External Ramp Compensation
Recommended Conditions: V
IN
=12V, I
OUT
=2A
V
OUT
(V)
L
(μH)
R1
(kΩ)
R2
(kΩ)
R7
(kΩ)
1.2 2.2 12.1 26.1 174
2.5 2.2 30 14.3 348
3.3 2.2 40.2 13.3 475
When output cap is ceramic caps with lower ESR,
external ramp is needed as shown in Fig.9.
Recommended parameters are as listed in Table
4 to Table 6 with R9=0.
Table 4—300kHz Recommended Parameters
with External Ramp Compensation
Recommended Conditions: V
IN
=12V, I
OUT
=2A
V
OUT
(V)
L
(μH)
R1
(kΩ)
R2
(kΩ)
R4
(kΩ)
C4
(pF)
R7
(kΩ)
1.2
3.3
12.1 26.1 330 220 402
2.5
3.3
30 14.3 698 220 820
3.3
3.3
40.2 12.7 698 220 1000
Table 5—500kHz Recommended Parameters
with External Ramp Compensation
Recommended Conditions: V
IN
=12V, I
OUT
=2A
V
OUT
(V)
L
(μH)
R1
(kΩ)
R2
(kΩ)
R4
(kΩ)
C4
(pF)
R7
(kΩ)
1.2
3.3
12.1 26.1 402 220 240
2.5
3.3
30 14.3 549 220 510
3.3
3.3
40.2 12.7 698 220 649
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

MP1492DS-LF

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Manufacturer:
Monolithic Power Systems (MPS)
Description:
Switching Voltage Regulators 2A 4.2-16V Fast Trns Synch Step-Down
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