18
LTC1417
sn1417 1417fas
Conversion Clock Selection
In Figure 15, the conversion clock controls the internal
ADC operation. The conversion clock can be either inter-
nal or external. By connecting EXTCLKIN high, the inter-
nal clock is selected. This clock generates 16 clock cycles
which feed into the SAR for each conversion.
To select an external conversion clock, apply an external
conversion clock to EXTCLKIN (Pin 6). (When an external
shift clock (SCLK) is used during a conversion, the SCLK
should be used as the external conversion clock to avoid
the noise generated by the asynchronous clocks. To
maintain accuracy, the external conversion clock fre-
quency must be between 50kHz and 9MHz.) The SAR
sends an end of conversion signal, EOC, that gates the
external conversion clock so that only 16 clock cycles can
go into the SAR, even if the external clock, EXTCLKIN,
contains more than 16 cycles.
When RD is low, these 16 cycles of conversion clock
(whether internally or externally generated) will appear
on CLKOUT during each conversion and then CLKOUT
will remain low until the next conversion. If desired,
CLKOUT can be used as a master clock to drive the serial
port. Because CLKOUT is running during the conversion,
it is important to avoid excessive loading that can cause
large supply transients and create noise. For the best
performance, limit CLKOUT loading to 20pF.
Serial Port
The serial port in Figure 15 is made up of a 16-bit shift
register and a three-state output buffer that are con-
trolled by two inputs: SCLK and RD. The serial port has
one output, D
OUT
, that provides the serial output data.
The SCLK is used to clock the shift register. Data may be
clocked out with the internal conversion clock operating
as a master by connecting CLKOUT (Pin 8) to SCLK
(Pin␣ 7) or with an external data clock applied to SCLK.
The minimum number of SCLK cycles required to trans-
fer a data word is 14. Normally, SCLK contains 16 clock
cycles for a word length of 16 bits; 14 bits with MSB first,
followed by two trailing zeros.
A logic high on RD disables SCLK and three-states D
OUT
.
In case of using a continuous SCLK, RD can be controlled
to limit the number of shift clocks to the desired number
(i.e., 16 cycles) and to three-state D
OUT
after the data
transfer.
In power shutdown mode (SHDN = low), a high RD
selects Sleep mode while a low RD selects Nap mode.
D
OUT
outputs the serial data; 14 bits, MSB first, on the
falling edge of each SCLK (see Figures 16 and 17). If 16
SCLKs are provided, the 14 data bits will be followed by
two zeros. The MSB (D13) will be valid on the first rising
and the first falling edge of the SCLK. D12 will be valid on
the second rising and the second falling edge as will all
the remaining bits. The data may be captured using either
edge. The largest hold time margin is achieved if data is
captured on the rising edge of SCLK.
BUSY gives the end-of-conversion indication. When the
LTC1417 is configured as a serial bus master, BUSY can
be used as a framing pulse. To three-state the serial port
after transferring the serial output data, BUSY and RD
should be connected together at the ADC (see Figure 17).
Figures 17 to 20 show several serial modes of operation,
demonstrating the flexibility of the LTC1417 serial interface.
APPLICATIONS INFORMATION
WUU
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Figure 16. SCLK to D
OUT
Delay
t
12
t
11
SCLK
V
IL
V
OH
V
OL
D
OUT
1417 F16
