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LTC1417IGN#TRPBF

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19
LTC1417
sn1417 1417fas
APPLICATIONS INFORMATION
WUU
U
Figure 17. Internal Conversion Clock Selected. Data Transferred During Conversion Using
the ADC Clock Output as a Master Shift Clock (SCLK Driven from CLKOUT)
D12 D11
D11D12
CAPTURE ON
RISING CLOCK
D13
D10D9D8D7D6D5D4D3D2D1D0
FILL
ZEROS
D13
1
t
2
t
3
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3
D13 D13 D12 D11
Hi-Z
Hi-Z
DATA NDATA (N – 1)
(SAMPLE N)
(SAMPLE N + 1)
D
OUT
EXTCLKIN = 5
CLKOUT (= SCLK)
CONVST
t
10
t
CONV
t
5
SAMPLE HOLDHOLD
t
7
t
4
t
8
1417 F17
BUSY (= RD)
t
12
t
11
CLKOUT
(= SCLK)
V
IL
V
OH
V
OL
D
OUT
CAPTURE ON
FALLING CLOCK
LTC1417
BUSY (= RD)
CLKOUT ( = SCLK)
BUSYCONVSTCONVST
RD
SCLK
CLKOUT
D
OUT
1413
12
7
8
9
D
OUT
µP OR DSP
(CONFIGURED
AS SLAVE)
OR
SHIFT
REGISTER
Serial Data Output During a Conversion
Using Internal Clock for Conversion and Data Transfer.
Figure 17 shows data from the previous conversion being
clocked out during the conversion with the LTC1417
internal clock providing both the conversion clock and the
SCLK. The internal clock has been optimized for the fastest
conversion time; consequently, this mode can provide the
best overall speed performance. To select the internal
conversion clock, tie EXTCLKIN (Pin 6) high. The internal
clock appears on CLKOUT (Pin 8) which can be tied to
SCLK (Pin 7) to supply the SCLK.
20
LTC1417
sn1417 1417fas
Using External Clock for Conversion and Data Transfer.
In Figure 18, data from the previous conversion is output
during the conversion with an external clock providing
both the conversion clock and the shift clock. To select an
external conversion clock, apply the clock to EXTCLKIN.
The same clock is also applied to SCLK to provide a data
APPLICATIONS INFORMATION
WUU
U
Figure 18. External Conversion Clock Selected. Data Transferred During Conversion Using
the External Clock (External Clock Drives Both EXTCLKIN and SCLK)
shift clock. To maintain conversion accuracy, the external
clock frequency must be between 50kHz and 9MHz.
Using an external clock to transfer data while an internal
clock controls the conversion process is not recom-
mended. As both signals are asynchronous, clock noise
can corrupt the conversion result.
D12 D11
D11D12
CAPTURE ON
RISING CLOCK
D13
D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
FILL
ZEROS
D13
1
t
2
t
3
t
7
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3
D13 D13 D12 D11
Hi-Z
Hi-Z
DATA NDATA (N – 1)
(SAMPLE N)
(SAMPLE N + 1)
D
OUT
EXTCLKIN (= SCLK)
CONVST
t
10
t
CONV
t
5
SAMPLE HOLDHOLD
t
dEXTCLKIN
t
4
t
8
1417 F18
BUSY (= RD)
t
12
t
11
t
LEXTCLKIN
t
HEXTCLKIN
EXTCLKIN
(= SCLK)
V
IL
V
OH
V
OL
D
OUT
CAPTURE ON
FALLING CLOCK
LTC1417
BUSY (= RD)
EXTCLKIN ( = SCLK)
BUSYCONVSTCONVST
RD
EXTCLKIN
SCLK
D
OUT
D
OUT
9
1413
7
6
12
µP OR DSP
21
LTC1417
sn1417 1417fas
1211109876543210
FILL
ZEROS
D13
t
2
t
3
12345678910111213141516
Hi-Z
DATA N
Hi-Z
(SAMPLE N)
D
OUT
EXTCLKIN = 5
CONVST
t
10
t
CONV
t
5
HOLD
SAMPLE
t
6
t
7
t
9
1417 F19
t
8
BUSY
SCLK
RD
D11D12
CAPTURE ON
RISING CLOCK
D13
t
12
t
11
t
LSCLK
t
HSCLK
SCLK
V
IL
V
OH
V
OL
D
OUT
CAPTURE ON
FALLING CLOCK
LTC1417
BUSYCONVST
1413
9
12
7
CONVST
RD
SCLK
D
OUT
µP OR DSP
INT
C0
SCK
MISO
APPLICATIONS INFORMATION
WUU
U
Figure 19. Internal Conversion Clock Selected. Data Transferred After Conversion
Using an External SCLK. BUSY↑ Indicates End of Conversion
MICROWIRE is a trademark of National Semiconductor Corporation.
Serial Data Output After a Conversion
Using an Internal Conversion Clock and an External Data
Clock. In this mode, data is output after the end of each
conversion and before the next conversion is started
(Figure 19). The internal clock is used as the conversion
clock and an external clock is used for the SCLK. This
mode is useful in applications where the processor acts as
a serial bus master device. This mode is SPI and
MICROWIRE
TM
compatible. It also allows operation when
the SCLK frequency is very low (less than 30kHz). To
select the internal conversion clock, tie EXTCLKIN high.
The external SCLK is applied to SCLK. RD can be used to
gate the external SCLK, such that data will clock only after
RD goes low and to three-state D
OUT
after data transfer. If
more than 16 SCLKs are provided, more zeros will be filled
in after the data word indefinitely.
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LTC1417IGN#TRPBF

Mfr. #:
Buy LTC1417IGN#TRPBF
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC L Pwr 14-B, 400ksps Smpl ADC Conv w/ Ser
Lifecycle:
New from this manufacturer.
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