MAX5132/MAX5133
+5V/+3V, 13-Bit, Serial, Force/Sense DACs
with 10ppm/°C Internal Reference
______________________________________________________________________________________ 13
PIC16 with SSP Module
and PIC17 Interface
The MAX5132/MAX5133 are compatible with a
PIC16/PIC17 microcontroller (µC), using the synchro-
nous serial port (SSP) module. To establish SPI com-
munication, connect the controller as shown in Figure 4
and configure the PIC16/PIC17 as system master by
initializing its synchronous serial-port control register
(SSPCON) and synchronous serial-port status register
(SSPSTAT) to the bit patterns shown in Tables 3 and 4.
In SPI mode, the PIC16/PIC17 µCs allow eight bits of
data to be synchronously transmitted and received
simultaneously. Two consecutive 8-bit writings (Figure
6) are necessary to feed the DAC with three control bits
and 13 data bits. DIN data transitions on the serial
clock’s falling edge and is clocked into the DAC on
SCLK’s rising edge. The first eight bits of DIN contain
the three control bits (C2, C1, C0) and the first five data
bits (D12–D8). The second 8-bit data stream contains
the remaining bits, D7–D0.
Serial Data Output
The contents of the internal shift-register are output seri-
ally on DOUT, which allows for daisy-chaining (see
Applications Information
) of multiple devices as well as
data readback. The MAX5132/MAX5133 may be pro-
grammed to shift data out of DOUT on the serial clock’s
rising edge (Mode 1) or on the falling edge (Mode 0).
The latter is the default during power-up and provides a
lag of 16 clock cycles, maintaining SPI, QSPI,
MICROWIRE, and PIC16/PIC17 compatibility. In Mode
1, the output data lags DIN by 15.5 clock cycles.
During power-down, DOUT retains its last digital state
prior to shutdown.
User-Programmable Output (UPO)
The UPO feature allows an external device to be con-
trolled through the serial-interface setup (Table 1),
thereby reducing the number of microcontroller I/O
ports required. During power-down, this output will
retain the last digital state before shutdown. With CLR
pulled low, UPO will reset to the default state after
wake-up.
CS
SCLK
DIN
COMMAND
EXECUTED
9
8
16
1
C1
C2 D0
C0
D12
D11
D10
D9 D6 D5 D4 D3 D2 D1D8 D7
Figure 6. Serial-Interface Timing
SCLK
DIN
DOUT
t
CS0
t
CSS
t
CL
t
CH
t
CP
t
CSW
t
CS1
t
CSH
t
DS t
DO1
t
DO2
t
DH
CS
Figure 7. Detailed Serial-Interface Timing
Table 2. Serial Data Format
C2, C1, C0 D12................................D0
16 BITS OF SERIAL DATA
MSB ...........................................LSB
MSB ..... Data Bits ..... LSB
Control Bits
MAX5132/MAX5133
+5V/+3V, 13-Bit, Serial, Force/Sense DACs
with 10ppm/°C Internal Reference
14 ______________________________________________________________________________________
__________Applications Information
Definitions
Integral Nonlinearity (INL)
Integral nonlinearity (Figure 8a) is the deviation of the
values on an actual transfer function from a straight
line. This straight line can be either a best-straight-line
fit (closest approximation to the actual transfer curve) or
a line drawn between the endpoints of the transfer func-
tion, once offset and gain errors have been nullified. For
a DAC, the deviations are measured at every single
step.
Differential Nonlinearity (DNL)
Differential nonlinearity (Figure 8b) is the difference
between an actual step height and the ideal value of
1LSB. If the magnitude of the DNL is less than or equal to
1LSB, the DAC guarantees no missing codes and is
monotonic.
Offset Error
The offset error (Figure 8c) is the difference between
the ideal and the actual offset point. For a DAC, the off-
set point is the step value when the digital input is zero.
This error affects all codes by the same amount and
can usually be compensated for by trimming.
Table 3. Detailed SSPCON Register Contents
X = Don’t care
Table 4. Detailed SSPSTAT Register Contents
X = Don’t care
SSPM3 0
Synchronous Serial-Port Mode Select Bit. Sets SPI master mode
and selects f
CLK
= f
OSC
/ 16.
MAX5132/MAX5133
SETTINGS
SYNCHRONOUS SERIAL-PORT CONTROL REGISTER
(SSPCON)
WCOL X Write-Collision Detection Bit
SSPM1 0
CONTROL BIT
BIT1
BIT0SSPM0 1
BIT3
BIT2SSPM2 0
SSPEN 1
Synchronous Serial Port Enable Bit
0: Disables serial port and configures these pins as I/O port pins.
1: Enables serial port and configures SCK, SDO, and SCI as seri-
al-port pins.
BIT5
BIT4CKP 0 Clock-Polarity Select Bit. CKP = 0 for SPI master-mode selection.
BIT7
BIT6SSPOV X Receive-Overflow Detection Bit
S X Start Bit
MAX5132/MAX5133
SETTINGS
SYNCHRONOUS SERIAL-PORT STATUS REGISTER
(SSPSTAT)
SMP 0
SPI Data-Input Sample Phase. Input data is sampled at the mid-
dle of the data-output time.
UA X
CONTROL BIT
BIT1
BIT0BF X
BIT3
BIT2R/W X
D/A X Data-Address BitBIT5
BIT4P X Stop Bit
Read/Write Bit Information
Update Address
BIT7
Buffer Full-Status Bit
BIT6CKE 1
SPI Clock-Edge Select Bit. Data will be transmitted on the rising
edge of the serial clock.
MAX5132/MAX5133
+5V/+3V, 13-Bit, Serial, Force/Sense DACs
with 10ppm/°C Internal Reference
______________________________________________________________________________________ 15
Gain Error
Gain error (Figure 8d) is the difference between the
ideal and the actual full-scale output voltage on the
transfer curve, after nullifying the offset error. This error
alters the slope of the transfer function and corre-
sponds to the same percentage error in each step.
Settling Time
The settling time is the amount of time required from the
start of a transition until the DAC output settles to its new
output value within the converter’s specified accuracy.
Digital Feedthrough
Digital feedthrough is noise generated on the DAC’s
output when any digital input transitions. Proper board
layout and grounding will significantly reduce this
noise, but there will always be some feedthrough
caused by the DAC itself.
Unipolar Output
Figure 9 shows the MAX5132/MAX5133 setup for
unipolar, Rail-to-Rail™ operation with a closed-loop
gain of 2V/V. With its internal reference of +2.5V, the
MAX5132 provides a convenient unipolar output range
of 0 to +4.99939V, while the MAX5133 offers an output
range of 0 to +2.499695V with its on-board +1.25V ref-
erence. Table 5 lists example codes for unipolar output
voltages.
Bipolar Output
The MAX5132/MAX5133 can be configured for unity-
gain bipolar operation (FB = OUT) using the circuit
shown in Figure 10. The output voltage V
OUT
is then
given by the following equation:
V
OUT
= V
REF
[G (NB / 8192) - 1]
0
2
1
4
3
7
6
5
000 010001 011 100 101 110
AT STEP
011 (1/2 LSB )
AT STEP
001 (1/4 LSB )
111
DIGITAL INPUT CODE
ANALOG OUTPUT VALUE (LSB)
Figure 8a. Integral Nonlinearity
Figure 8b. Differential Nonlinearity
0
2
1
4
3
6
5
000 010001 011 100 101
DIFFERENTIAL LINEARITY
ERROR (-1/4 LSB)
DIFFERENTIAL
LINEARITY ERROR (+1/4 LSB)
1 LSB
1 LSB
DIGITAL INPUT CODE
ANALOG OUTPUT VALUE (LSB)
0
2
1
3
000 010001 011
ACTUAL
DIAGRAM
IDEAL DIAGRAM
ACTUAL
OFFSET POINT
OFFSET ERROR
(+1 1/4 LSB)
IDEAL OFFSET
POINT
DIGITAL INPUT CODE
ANALOG OUTPUT VALUE (LSB)
Figure 8c. Offset Error
Figure 8d. Gain Error
0
5
4
6
7
000 101100 110 111
IDEAL DIAGRAM
GAIN ERROR
(-1 1/4 LSB)
IDEAL FULL-SCALE OUTPUT
ACTUAL
FULL-SCALE
OUTPUT
DIGITAL INPUT CODE
ANALOG OUTPUT VALUE (LSB)
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.

MAX5132AEEE+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Digital to Analog Converters - DAC 13-Bit 2Ch Precision DAC
Lifecycle:
New from this manufacturer.
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