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FEATURES
§ Four independent, digitally controlled 64-
position potentiometers
§ Two interface control options
- 5-wire serial
- 2-wire addressable
§ Standard resistance values
- DS1844-010 10 kW
- DS1844-050 50 kW
- DS1844-100 100 kW
§ Mixed resistor value combinations (contact
factory for availability)
§ Operating Temperature Range
- Industrial: -40°C to +85°C
PIN ASSIGNMENT
PIN DESCRIPTION
V
CC
- 2.7V to 5.5V
PS - Port Select
A0, A1, A2 - Device Select Pins (2-Wire)
SDA - Serial Data I/O (2-Wire)
SCL - Serial Clock (2-Wire)
R/ W - Read/Write enable (5-Wire)
RST - Serial Port Reset Input (5-Wire)
D
IN
- Serial Port Data Input (5-Wire)
CLK - Serial Port Clock Input (5-Wire)
D
OUT
- Cascade Data Output (5-Wire)
H
0
-H
3
- High-end Terminal of Pot
L
0
-L
3
- Low-end Terminal of Pot
W
0
-W
3
- Wiper Terminal of Pot
GND - Ground
DESCRIPTION
The DS1844 Quad Digital Potentiometer is a four-channel, digitally controlled linear potentiometer. Each
potentiometer is comprised of 63 equi-resistive sections and has three terminals accessible to the user.
These include the high side terminals, H
X
, the wiper terminals, W
X
, and the low-side terminals, L
X.
The
wiper position on the resistor ladder is selected via an 8-bit register value. Communication and control of
the device are supported by two types of serial interface. These include a 5-wire I/O shift register
interface and a 2-wire addressable interface.
DS1844
Quad Digital Potentiomete
r
www.maxim-ic.com
Device Description
PS 1 20 V
CC
H2 2 19 H1
H3 3 18 H0
W3 4 17 W0
L3 5 16 L0
L2 6 15 L1
W2 7 14 W1
R/W, A0 8 13 SCL, CLK
A2, RST 9 12 SDA, D
IN
GND 10 11 A1, D
OUT
20-Pin DIP (300-mil)
20-Pin SOIC (300-mil)
20-Pin TSSOP (173-mil)
DS1844
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The DS1844 is available in standard 10 kW, 50 kW, and 100 kW versions. Mixed resistor combinations
are also available through custom setups. The DS1844 is specified to operate over the industrial
temperature range: -40°C to +85°C. Packages for the DS1844 include 20-pin DIPs, SOICs, and TSSOPs.
OPERATION
The DS1844 contains four 64-position potentiometers. Each potentiometer is independent and has three
accessible terminals, which include H
X
, L
X
, and W
X
. Each potentiometer is comprised of 63 individual
resistor elements. Between each resistor element is a tap-point that is multiplexed to the wiper terminal,
W
X
. Additionally, the wiper terminal can be multiplexed directly to the end-terminals, H
X
and L
X
.
The DS1844 supports two interface control options. Both options allow for the direct placement of the
wiper position on the resistor ladder. Each wiper has an associated 6-bit register used to hold its positional
value.
The DS1844 is a volatile device and will always power-up with the wiper positions set to mid-tap
(position 32-decimal). The end-terminal H
X
will have wiper position value 63-decimal and the L
X
terminal
will have wiper position value 0-decimal. Because the DS1844 is a 64-position device only 6 bits of data
are necessary to write a wiper’s value. However, communication with the DS1844 will require using a
full 8 bits, with the remaining 2 bits specifying the potentiometer selected. A discussion of proper
communication protocol is provided under the section entitled Serial Port Operation. A block diagram of
the DS1844 is shown in Figure 1.
SERIAL PORT OPERATION
As stated, the DS1844 can support two types of serial interface control. This includes a 5-wire serial
interface and a 2-wire addressable interface. The type interface supported during operation is selectable
via the port select input pin, PS. Additionally, certain pins provide dual functionality dependent on the
serial port selected. The pin description table lists pin functionality according to the interface selected.
5-Wire Serial Port Control
The 5-wire serial interface provides an 8-bit I/O shift register for loading and reading wiper data. The 5-
wire serial interface control is selected when the port select input, PS, is in a low state. This interface is
controlled by the signals
RST , DIN, DOUT, CLK, and R/ W . Timing diagrams for the 5-wire serial port
can be found in Figure 3. Timing information for the 5-wire serial port is provided in the AC Electrical
Characteristics table for 5-wire serial communications.
Data is loaded MSB first and in multiples of 8 bits. The 8-bit data to specify wiper position has the format
or protocol as that shown in Figure 2. The 8-bit data is divided into potentiometer select data and wiper
position value. The 6 least significant bits of data specify the wiper position value while the 2 most
significant bits specify the potentiometer to be loaded. This allows the interface control logic/protocol to
provide order independent potentiometer loading, as well as variable-length data loads.
As stated earlier, the 5-wire serial port is selected when the PS input is in a low state. If the device will
only be used in the 5-wire mode, the PS input can be tied directly to ground. Communication via the 5-
wire interface is enabled when
RST is in a high state. A low-to-high transition on the RST indicates the
start of a communication transaction with the DS1844. While RST is high, data can be read or written to
the part. Data will be read or written dependent on the state of the read-write enable input, R/ W . The
state of R/ W must be stable before a low-to-high transition on RST . Once the RST input has begun a
communication transaction, the serial port will ignore any transitions on the R/ W input.
DS1844
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When writing data, the R/ W input should be in a low state. Once RST has activated the port, a data bit is
latched (or valid) on the low-to-high transition of the CLK signal. Once, eight low-to-high transitions
have occurred on the CLK input, the associated 8-bit data block will be loaded as the wiper’s value on the
falling edge of the eighth clock pulse. Potentiometer wiper values can be loaded in any order. Also,
potentiometer wiper data can be loaded 1, 2, 3, or 4 bytes at a time. When RST transitions from high to
low, the 5-wire port will be disabled.
While RST is high and R/ W is low, (the write or load state) the cascade data output, D
OUT
will be
inhibited; preventing the passing of data from D
IN
to D
OUT
. However, when RST is low data is passed
directly from D
IN
to D
OUT
.
When reading data, the R/ W input should be in a high state. Once RST has enabled the port, data can be
clocked out of the device and will appear on the D
OUT
terminal. A data bit will be valid on the falling
edge of a clock pulse after a maximum time period of 20 ns (of that falling edge). Data will appear on
D
OUT
most significant bit (MSB) first and starting with potentiometer-0, followed by potentiometer-1 and
so forth.
2-Wire Addressable Serial Port Control
The 2-wire serial port interface supports a bi-directional data transmission protocol with device
addressing. A device that sends data on the bus is defined as a transmitter, and a device receiving data as
a receiver. The device that controls the message is called a “master.” The devices that are controlled by
the master are “slaves.” The bus must be controlled by a master device which generates the serial clock
(SCL), controls the bus access, and generates the START and STOP conditions. The DS1844 operates as
a slave on the two-wire bus. Connections to the bus are made via the open-drain I/O lines SDA and SCL.
The 2-wire serial port is selected when the port select input, PS, is in a high-state. The following I/O
terminals control the 2-wire serial port: SDA, SCL, A0, A1, A2, PS=1. Timing diagrams for the 2-wire
serial port can be found in Figures 4 through 8. Timing information for the 2-wire serial port is provided
in the AC Electrical Characteristics table for 2-wire serial communications.
The following bus protocol has been defined (See Figure 4).
- Data transfer may be initiated only when the bus is not busy.
- During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes
in the data line while the clock line is high will be interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus not busy: Both data and clock lines remain HIGH.
Start data transfer: A change in the state of the data line from HIGH to LOW while the clock is HIGH
defines a START condition.
Stop data transfer: A change in the state of the data line from LOW to HIGH while the clock line is
HIGH defines the STOP condition.

DS1844S-010+

Mfr. #:
Manufacturer:
Description:
Digital Potentiometer ICs Quad
Lifecycle:
New from this manufacturer.
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