DS1844
9 of 14
5-WIRE SERIAL INTERFACE
AC ELECTRICAL CHARACTERISTICS (-40°C to +85°C; V
CC
=2.7V to 5.5V)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Port Select Setup t
SETUP
30 ns 14, 21
R/ W Setup
t
SETUP
30
ns
14, 21
Clock Frequency f
CLK
DC
5
MHz
14, 15
Width of CLK Pulse t
CH
50
ns 14, 15
Data Setup Time t
DC
30
ns 14, 15
Data Hold Time t
CDH
0
ns 14, 15
Progapation Delay Time High to Low
Level Clock to Output
t
DV
40 ns 14, 15
RST High to Clock Input High
t
CC
50
ns 14, 15
RST Low from Clock Input High
t
HLT
50
ns 14, 15
RST Inactive
t
RLT
125
ns 14, 15
CLK Rise Time, CLK Fall Time t
CR
50 ns 14, 15
NOTES:
1. All voltages are referenced to ground.
2. I/O pins of fast mode devices must not obstruct the SDA and SCL lines if V
CC
is switched off.
3. I
CC
specified with SDA pin open.
4. I
STBY
specified with for V
CC
equal 3.0V and 5.0V and control port logic pins are driven to the
appropriate logic levels. Appropriate logic levels specify that logic inputs are within a 0.5-volt of
ground or V
CC
for the corresponding inactive state.
5. After this period, the first clock pulse is generated.
6. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the
V
IH MIN
of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
7. The maximum t
HD:DAT
has only to be met if the device does not stretch the LOW period (t
LOW
) of
the SCL.
8. A fast mode device can be used in a standard mode system, but the requirement t
SU:DAT
> 250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW
period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must
output the next data bit to the SDA line t
RMAX
+ t
SU:DAT
= 1000+250=1250 ns before the SCL line
is released.
9. C
B
- total capacitance of one bus line in picofarads, timing referenced to (0.9)(V
CC
) and (0.1)
(V
CC
).
10. Typical values are for ta = 25°C and nominal supply voltage.
