Technical Note
5/18
BU6520KV,BU6521KV
www.rohm.com
2010.02 - Rev.C
© 2010 ROHM Co., Ltd. All rights reserved.
PIN
No.
PIN Name In/Out
Active
Level
Init Function explanation
Power
Source
System
I/O
type
*1
25 CAMHSO Out * Low Horizontal timing output 1 F
26 CAMVSO Out * Low Vertical timing output 1 F
27 CAMCKO Out CLK Low Clock output 1 F
28 GND - GND - Common GROUND 1,2,4 -
29 VDD - PWR - CORE power source 4 -
30 AUTO In High PD
*2
Auto register setting enable signal 1 D
31 MODE0 In DATA PD
*2
Auto register setting mode select bit 0 1 D
32 MODE1 In DATA PD
*2
Auto register setting mode select bit 1 1 D
33 VOUT Out Analog - Analog composite output 3 H
34 AVSS - GND - Analog GROUND for DAC 3 -
35 IREF Out Analog - Reference voltage for DAC 3 I
36 AVDD - PWR - Analog power source for DAC 3 -
37 GND - GND - Common GROUND 1,2,4 -
38 VDDI2C - PWR -
Digital IO power source
(For 2-line serial interface input/output)
2 -
39 SDA In/Out DATA In 2-line serial interface data input/output 2 G
40 SDC In/Out CLK In 2-line serial interface clock input 2 G
41 RESETB In Low - System reset signal 1 B
42 TEST In High PD
*2
Test mode terminal (Connect to GND) 1 D
43 GND - GND - Common GROUND 1,2,4 -
44 VDDIO - PWR - Digital IO power source 1 -
45 WPB Out Low Low Write protect signal to EEPROM 1 F
46 SCEB Out Low High Chip select signal to EEPROM 1 F
47 SCK Out CLK Low SPI-bus clock 1 F
48 SDO Out DATA Low SPI-bus data output 1 F
※ ” * ” in the Active Level column indicates that it may be changed during set-up of the register.
※ Init column indicates pin status when released from reset.
※ In the power system column, ” 1 ” stands for VDDIO, ” 2 ” stands for VDDI2C, ” 3 ” stands for AVDD, ” 4 ” stands for VDD.
*1 Fig.3 Equivalent Circuit Structures of input / output pins reference
*2 Pull-down status.
