ADRF5026 Data Sheet
Rev. 0 | Page 4 of 13
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
DIGITAL CONTROL INPUTS CTRL and EN pins
Voltage
Low V
INL
0 0.8 V
High V
INH
1.2 3.3 V
Current
Low and High Current I
INL
, I
INH
<1 μA
RECOMMENDED OPERATING
CONDITONS
Supply Voltage
Positive VDD 3.15 3.45 V
Negative VSS −3.45 −3.15 V
Digital Control Voltage V
CTRL
, V
EN
0 VDD V
RF Input Power
3
P
IN
f = 100 MHz to 40 GHz, T
CASE
= 85°C
4
Insertion Loss Path
RF signal is applied to the RFC or through
connected RF1/RF2
24 dBm
Isolation Path RF signal is applied to terminated RF1/RF2 24 dBm
Hot Switching
RF signal is present at the RFC while switching
between RF1 and RF2
24 dBm
Case Temperature T
CASE
−40 +105 °C
1
Impendence matching on RF transmission lines improves high frequency performance. Refer to the Applications Information section for more information.
2
For input linearity performance vs. frequency, see Figure 11 and Figure 13.
3
For power derating vs. frequency, see Figure 2 and Figure 3. This power derating is applicable for insertion loss path, isolation path, and hot switching power
specifications.
4
For 105°C operation, the power handling degrades from the T
CASE
= 85°C specification by 3 dB.
Data Sheet ADRF5026
Rev. 0 | Page 5 of 13
ABSOLUTE MAXIMUM RATINGS
For recommended operating conditions, see Table 1.
Table 2.
Parameter Rating
Positive Supply Voltage −0.3 V to +3.6 V
Negative Supply Voltage −3.6 V to +0.3 V
Digital Control Input Voltage −0.3 V to VDD +0.3 V
RF Input Power
1
(100 MHz to 40 GHz at
T
CASE
= 85°C
2
)
Insertion Loss Path 26 dBm
Isolation Path 25 dBm
Hot Switching 25 dBm
Temperature
Junction, T
J
135°C
Storage Range −65°C to +150°C
Reflow 260°C
Electrostatic Discharge (ESD) Sensitivity
Human Body Model (HBM)
RFC, RF1, RF2 Pins 500 V
Digital Pins 2000 V
Charged Device Model (CDM) 1250 V
1
For power derating vs. frequency, see Figure 2 and Figure 3. This power
derating is applicable for insertion loss path, isolation path, and hot
switching power specifications.
2
For 105°C operation, the power handling degrades from the T
CASE
= 85°C
specification by 3 dB.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Only one absolute maximum rating can be applied at any one
time.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θ
JC
is the junction to case bottom (channel to package bottom)
thermal resistance.
Table 3. Thermal Resistance
Package Type θ
JC
Unit
CC-20-3
Through Path 423 °C/W
Terminated Path 241 °C/W
POWER DERATING CURVES
2
–14
–12
–10
–8
–6
–4
–2
0
10k 100k 1M 10M 100M 1G 10G 100G
POWER DERATING (dB)
FREQUENCY (Hz)
16767-002
Figure 2. Power Derating vs. Frequency, Low Frequency Detail, T
CASE
= 85°C
2
–12
–10
–8
–6
–4
–2
0
30 32 34 36 38 40 42 44 46 48 50
POWER DERATING (dB)
FREQUENCY (GHz)
16767-003
Figure 3. Power Derating vs. Frequency, High Frequency Detail, T
CASE
= 85°C
ESD CAUTION
ADRF5026 Data Sheet
Rev. 0 | Page 6 of 13
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
G
N
D
R
F
2
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
R
F
1
GND
GND
RFC
GND
GND
VSS
EN
GND
CTRL
VDD
1
2
3
4
5
6
7
8910
11
12
13
1617181920
15
14
G
N
D
G
N
D
ADRF5026
TOP VIEW
(Not to Scale)
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED
TO RF AND DC GROUND OF THE PCB.
16767-004
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1, 2, 4, 5, 6, 7, 9, 10,
13, 16, 17, 19, 20
GND Ground. These pins must be connected to the RF and dc ground of the PCB.
3 RFC
RF Common Port. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is
necessary when the RF line potential is equal to 0 V dc. See Figure 5 for the interface schematic.
8 RF1
RF1 Port. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is necessary
when the RF line potential is equal to 0 V dc. See Figure 5 for the interface schematic.
11 VDD Positive Supply Voltage.
12 CTRL Control Input Voltage. See Table 5 for the truth table. See Figure 6 for the interface schematic.
14 EN Enable Input Voltage. See Table 5 for the truth table. See Figure 6 for the interface schematic.
15 VSS Negative Supply Voltage.
18 RF2
RF2 Port. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is necessary
when the RF line potential is equal to 0 V dc. See Figure 5 for the interface schematic.
EPAD Exposed Pad. The exposed pad must be connected to the RF and dc ground of the PCB.
INTERFACE SCHEMATICS
RFC,
RF1,
RF2
16767-005
Figure 5. RFC, RF1, RF2 Interface Schematic
V
DD
VDD
CTRL, EN
16767-006
Figure 6. CTRL, EN Interface Schematic

ADRF5026BCCZN

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
RF Switch ICs High isolation SP DT,40GHz,fast switch
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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