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ADRF5026BCCZN

P1-P3P4-P6P7-P9P10-P12P13-P13
Data Sheet ADRF5026
Rev. 0 | Page 7 of 13
TYPICAL PERFORMANCE CHARACTERISTICS
INSERTION LOSS, RETURN LOSS, AND ISOLATION
VDD = 3.3 V, VSS = −3.3 V, V
CTRL
/V
EN
= 0 V or VDD, and T
CASE
= 25°C in a 50 Ω system, unless otherwise noted.
Insertion loss and return loss are measured on the probe matrix board using ground-signal-ground (GSG) probes close to the RFx pins.
Signal coupling between the probes limits the isolation performance of ADRF5026. Isolation is measured on the ADRF5026-EVALZ
evaluation board. See the Applications Information section for details on the ADRF5026-EVALZ evaluation board and probe matrix board.
0
–8
–7
–6
–5
–4
–3
–2
–1
0 5 10 15 20 25 30 35 40 45 50
INSERTION LOSS (dB)
FREQUENCY (GHz)
RF2, T
CASE
= 25°C
RF1, T
CASE
= 25°C
16767-009
Figure 7. Insertion Loss vs. Frequency at Room Temperature for RF1 and RF2
0
–40
–35
–30
–25
–20
–15
–10
–5
0 5 10 15 20 25 30 35 40 45 50
RETURN LOSS (dB)
FREQUENCY (GHz)
RF1/RF2 OFF
RF1/RF2 ON
RFC
16767-010
Figure 8. Return Loss vs. Frequency
0
–8
–7
–6
–5
–4
–3
–2
–1
0 5 10 15 20 25 30 35 40 45 50
INSERTION LOSS (dB)
FREQUENCY (GHz)
T
CASE
= –40°C
T
CASE
= +25°C
T
CASE
= +85°C
T
CASE
= +105°C
16767-007
Figure 9. Insertion Loss vs. Frequency over Temperature
0
–80
–70
–60
–50
–40
–30
–20
–10
0 5 10 15 20 25 30 35 40 45 50
ISOLATION (dB)
FREQUENCY (GHz)
RF1 TO RF2
RFC TO RF1/RF2
16767-008
Figure 10. Isolation vs. Frequency
ADRF5026 Data Sheet
Rev. 0 | Page 8 of 13
INPUT POWER COMPRESSIONS AND THIRD-ORDER INTERCEPT
VDD = 3.3 V, VSS = −3.3 V, V
CTRL
/V
EN
= 0 V or VDD, and T
CASE
= 25°C in a 50 Ω system, unless otherwise noted. All of the large signal
performance parameters are measured on the ADRF5026-EVALZ evaluation board.
30
10
12
14
16
18
20
22
24
26
28
0 5 10 15 20 25 30 35 40
INPUT P1dB (dBm)
FREQUENCY (GHz)
16767-011
Figure 11. Input P1dB vs. Frequency
60
20
25
30
35
40
45
50
55
0 5 10 15 20 25 30 35 40
INPUT IP3 (dBm)
FREQUENCY (GHz)
16767-012
Figure 12. Input IP3 vs. Frequency
30
28
26
24
22
20
18
16
14
12
10
10k 100k 1M 10M 100M 1G
INPUT P1dB (dBm)
FREQUENCY (Hz)
16767-013
Figure 13. Input P1dB vs. Frequency (Low Frequency Detail)
60
20
25
30
35
40
45
50
55
10k 100k 1M 10M 100M 1G
INPUT IP3 (dBm)
FREQUENCY (Hz)
16767-014
Figure 14. Input IP3 vs. Frequency (Low Frequency Detail)
Data Sheet ADRF5026
Rev. 0 | Page 9 of 13
THEORY OF OPERATION
The ADRF5026 requires a positive supply voltage applied to the
VDD pin and a negative supply voltage applied to the VSS pin.
Bypassing capacitors are recommended on the supply lines to
filter high frequency noise.
All of the RF ports (RFC, RF1, and RF2) are dc-coupled to 0 V,
and no dc blocking capacitors are required at the RF ports when
the RF potential is equal to 0 V.
The RF ports are internally matched to 50 . Therefore,
external matching networks are not required. Impedance
matching on the RF transmission lines can improve insertion
loss and return loss performance at high frequencies.
The ADRF5026 integrates a driver to perform logic function
internally and to provide the advantage of a simplified control
interface. The driver features two digital control input pins,
CTRL and EN. When the EN pin is logic low, the logic level
applied to the CTRL pin determines which RF port is in
insertion loss state and which RF port is in isolation state.
The ADRF5026 supports an all off state control. When the EN
pin is logic high, both the RF1 to RFC path and the RF2 to RFC
path are in an isolation state, regardless of the logic state of the
CTRL pin. The RF1 and RF2 ports are terminated to internal
50 Ω resistors, and the RFC port becomes open reflective (see
Table 5).
The ADRF5026 design is bidirectional with equal power
handling capabilities. An RF input signal (RF
IN
) can be applied
to the RFC port or the RF1 or RF2 port. The isolation path
provides high loss between the unselected RFx port and the
insertion loss path.
The power-up sequence is as follows:
1. Power up GND.
2. Power up VDD.
3. Power up VSS.
4. Power up the digital control inputs. The relative order of
the logic control inputs is not important. Powering up the
digital control inputs before the VDD supply can
inadvertently forward bias and damage the internal ESD
protection structures.
5. Apply an RF input signal.
The power-down sequence is the reverse order of the power-up
sequence.
Table 5. Control Voltage Truth Table
Digital Control Input RF Paths
EN CTRL RF1 to RFC RF2 to RFC
Low Low Isolation (off) Insertion loss (on)
Low High Insertion loss (on) Isolation (off)
High Low Isolation (off) Isolation (off)
High High Isolation (off) Isolation (off)
P1-P3P4-P6P7-P9P10-P12P13-P13

ADRF5026BCCZN

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Buy ADRF5026BCCZN
Manufacturer:
Analog Devices Inc.
Description:
RF Switch ICs High isolation SP DT,40GHz,fast switch
Lifecycle:
New from this manufacturer.
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