LOW SKEW, 1-TO-11 DIFFERENTIAL-TO-3.3V LVPECL
CLOCK MULTIPLIER / ZERO DELAY BUFFER
8731-01 DATA SHEET
2 REVISION B 7/14/15
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
R
PULLUP
Input Pullup Resistor 51 kΩ
R
PULLDOWN
Input Pulldown Resistor 51 kΩ
Number Name Type Description
1 MR Input Pulldown
Active High Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs, Qx, to go low and the inverted outputs
nQx to go high. When logic LOW, the internal dividers and the outputs
are enabled. LVCMOS / LVTTL interface levels.
2, 10,
26, 36,
38, 48
V
CCO
Power Output supply pins.
3, 4,
5, 6
Q8, nQ8,
Q9, nQ9
Output Differential output pairs.
7, 14, 20,
31, 43
V
EE
Power Negative supply pins.
8,
9
Q10/FB_OUT,
nQ10/nFB_OUT
Output Differential clock outputs.
11, 12 FB_IN, nFB_IN Input Pulldown
Feedback input to phase detector for generating clocks with
“zero delay”.
15 V
CC
Power Core supply pin.
16 FB_SEL0 Input Pulldown
Determines output divider for Q10/FB outputs (see Table 3).
LVCMOS / LVTTL interface levels.
17 FB_SEL1 Input Pulldown
Determines output divider for Q10/FB outputs (see Table 3).
LVCMOS / LVTTL interface levels.
18 nREF_CLK Input Pullup Inverting differential clock input.
19 REF_CLK Input Pulldown Non-inverting differential clock input.
21 V
CCA
Power Analog supply pin.
22 DIV_SEL0, Input Pulldown
Determines output divider values in Table 3.
LVCMOS / LVTTL interface levels.
23 DIV_SEL1 Input Pulldown
Determines output divider values in Table 3.
LVCMOS / LVTTL interface levels.
24 DIV_SEL2 Input Pulldown
Determines output divider values in Table 3.
LVCMOS / LVTTL interface levels.
13, 25 nc Unused No connect.
27, 28
29, 30
Q0, nQ0,
Q1, nQ1
Output Differential output pairs.
32, 33,
34, 35
Q2, nQ2,
Q3, nQ3
Output Differential output pairs.
37 PLL_SEL Input Pullup
Selects between the PLL and reference clock as the input to the dividers.
When LOW, selects reference clock. When HIGH, selects PLL. LVCMOS
/ LVTTL interface levels.
39, 40,
41, 42
Q4, nQ4,
Q5, nQ5
Output Differential output pairs.
44, 45,
46, 47
Q6, nQ6,
Q7, nQ7
Output Differential output pairs.
NOTE:
Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
